[llvm] [AArch64] Teach areMemAccessesTriviallyDisjoint about scalable widths. (PR #73655)

[David Green via llvm-commits]

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@@ -3918,21 +3924,21 @@ bool AArch64InstrInfo::getMemOpInfo(unsigned Opcode, TypeSize &Scale,
   case AArch64::LD1RSH_S_IMM:
   case AArch64::LD1RSH_D_IMM:
     Scale = TypeSize::getFixed(2);
-    Width = 2;
+    Width = TypeSize::getFixed(2);
     MinOffset = 0;
     MaxOffset = 63;
     break;
   case AArch64::LD1RW_IMM:
   case AArch64::LD1RW_D_IMM:
   case AArch64::LD1RSW_IMM:
     Scale = TypeSize::getFixed(4);
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davemgreen wrote:

I believe they load a scalar and broadcast them to all lanes, so only load a fixed number of bytes is read from memory.

https://github.com/llvm/llvm-project/pull/73655