[llvm] [AArch64] Teach areMemAccessesTriviallyDisjoint about scalable widths. (PR #73655)
Harvin Iriawan via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 28 07:29:03 PST 2023
================
@@ -3918,21 +3924,21 @@ bool AArch64InstrInfo::getMemOpInfo(unsigned Opcode, TypeSize &Scale,
case AArch64::LD1RSH_S_IMM:
case AArch64::LD1RSH_D_IMM:
Scale = TypeSize::getFixed(2);
- Width = 2;
+ Width = TypeSize::getFixed(2);
MinOffset = 0;
MaxOffset = 63;
break;
case AArch64::LD1RW_IMM:
case AArch64::LD1RW_D_IMM:
case AArch64::LD1RSW_IMM:
Scale = TypeSize::getFixed(4);
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harviniriawan wrote:
aren't LD1RSW* SVE instructions as well? Any reasons why we don't change them to getScalable?
https://github.com/llvm/llvm-project/pull/73655
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