[llvm] a3ae7b6 - [RISCV] Minor style cleanup to cf17a24 [nfc]

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2023-11-28T07:27:30-08:00
New Revision: a3ae7b660acfac3a812fe366b9210a24bd383963

URL: https://github.com/llvm/llvm-project/commit/a3ae7b660acfac3a812fe366b9210a24bd383963
DIFF: https://github.com/llvm/llvm-project/commit/a3ae7b660acfac3a812fe366b9210a24bd383963.diff

LOG: [RISCV] Minor style cleanup to cf17a24 [nfc]

This was suggested in another related review, so backporting it to the
existing code as well.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index a417b6fe05e59df..c41d2e79d82129f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -7920,8 +7920,7 @@ SDValue RISCVTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
     MVT M1VT = getLMUL1VT(ContainerVT);
     unsigned OrigIdx = IdxC->getZExtValue();
     EVT ElemVT = VecVT.getVectorElementType();
-    unsigned ElemSize = ElemVT.getSizeInBits().getKnownMinValue();
-    unsigned ElemsPerVReg = MinVLen / ElemSize;
+    unsigned ElemsPerVReg = MinVLen / ElemVT.getFixedSizeInBits();
     unsigned RemIdx = OrigIdx % ElemsPerVReg;
     unsigned SubRegIdx = OrigIdx / ElemsPerVReg;
     unsigned ExtractIdx =