[llvm] GlobalISel lane masks merging (PR #73337)

[Petar Avramovic via llvm-commits]

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@@ -158,9 +153,9 @@ Register MachineSSAUpdater::GetValueInMiddleOfBlock(MachineBasicBlock *BB,
     if (ExistingValueOnly)
       return Register();
     // Insert an implicit_def to represent an undef value.
-    MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF,
-                                        BB, BB->getFirstTerminator(),
-                                        VRC, MRI, TII);
+    MachineInstr *NewDef =
+        InsertNewDef(TargetOpcode::IMPLICIT_DEF, BB, BB->getFirstTerminator(),
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petar-avramovic wrote:

Lane mask registers created in this pass are not generic, they have some sgpr register class and must also have S1 LLT. This is requirement for machine uniformity info to work correctly correctly.

https://github.com/llvm/llvm-project/pull/73337