[llvm] [RISCV] Split build_vector into vreg sized pieces when exact VLEN is known (PR #73606)

[Luke Lau via llvm-commits]

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@@ -3750,6 +3758,38 @@ static SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
   if (SDValue Res = lowerBuildVectorViaDominantValues(Op, DAG, Subtarget))
     return Res;
 
+  // If we're compiling for an exact VLEN value, we can split our work per
+  // register in the register group.
+  const unsigned MinVLen = Subtarget.getRealMinVLen();
+  const unsigned MaxVLen = Subtarget.getRealMaxVLen();
+  if (MinVLen == MaxVLen &&
+      VT.getSizeInBits().getKnownMinValue() > MinVLen) {
+    MVT ElemVT = VT.getVectorElementType();
+    unsigned ElemSize = ElemVT.getSizeInBits().getKnownMinValue();
----------------
lukel97 wrote:

Nit, could use an asserting method
```suggestion
    unsigned ElemSize = ElemVT.getFixedSizeInBits();
```

https://github.com/llvm/llvm-project/pull/73606