[llvm] [RISCV][GISel] Lower G_FCONSTANT to constant pool load without F or D. (PR #73034)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 27 20:42:54 PST 2023
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/73034
>From 6930114a71c2bdc872a7d4d46d18dfca921030f1 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 21 Nov 2023 12:03:39 -0800
Subject: [PATCH 1/2] [RISCV][GISel] Lower G_FCONSTANT to constant pool load
without F or D.
I used an IR test because it was easier than constructing different
MIR test for each type of addressing.
---
.../RISCV/GISel/RISCVInstructionSelector.cpp | 5 +-
.../Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 7 +-
.../CodeGen/RISCV/GlobalISel/constantpool.ll | 122 ++++++++++++++++++
3 files changed, 131 insertions(+), 3 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/constantpool.ll
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 9b4577dec87c570..8f8a4cccc705f73 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -532,6 +532,8 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
}
case TargetOpcode::G_JUMP_TABLE:
return selectAddr(MI, MIB, MRI);
+ case TargetOpcode::G_CONSTANT_POOL:
+ return selectAddr(MI, MIB, MRI);
case TargetOpcode::G_BRCOND: {
Register LHS, RHS;
RISCVCC::CondCode CC;
@@ -792,7 +794,8 @@ bool RISCVInstructionSelector::selectAddr(MachineInstr &MI,
bool IsLocal,
bool IsExternWeak) const {
assert((MI.getOpcode() == TargetOpcode::G_GLOBAL_VALUE ||
- MI.getOpcode() == TargetOpcode::G_JUMP_TABLE) &&
+ MI.getOpcode() == TargetOpcode::G_JUMP_TABLE ||
+ MI.getOpcode() == TargetOpcode::G_CONSTANT_POOL) &&
"Unexpected opcode");
const MachineOperand &DispMO = MI.getOperand(1);
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 0a73681acca27fe..bf84eab3c334295 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -188,7 +188,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
.widenScalarToNextPow2(0)
.clampScalar(0, sXLen, sXLen);
- getActionDefinitionsBuilder({G_GLOBAL_VALUE, G_JUMP_TABLE}).legalFor({p0});
+ getActionDefinitionsBuilder({G_GLOBAL_VALUE, G_JUMP_TABLE, G_CONSTANT_POOL})
+ .legalFor({p0});
if (ST.hasStdExtM() || ST.hasStdExtZmmul()) {
getActionDefinitionsBuilder(G_MUL)
@@ -273,7 +274,9 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
getActionDefinitionsBuilder(G_IS_FPCLASS)
.customIf(all(typeIs(0, s1), typeIsScalarFPArith(1, ST)));
- getActionDefinitionsBuilder(G_FCONSTANT).legalIf(typeIsScalarFPArith(0, ST));
+ getActionDefinitionsBuilder(G_FCONSTANT)
+ .legalIf(typeIsScalarFPArith(0, ST))
+ .lowerFor({s32, s64});
getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
.legalIf(all(typeInSet(0, {s32, sXLen}), typeIsScalarFPArith(1, ST)))
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/constantpool.ll b/llvm/test/CodeGen/RISCV/GlobalISel/constantpool.ll
new file mode 100644
index 000000000000000..1eeeb60c2eb4051
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/constantpool.ll
@@ -0,0 +1,122 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=riscv32 -global-isel -code-model=small \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=RV32-SMALL
+; RUN: llc < %s -mtriple=riscv32 -global-isel -code-model=medium \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=RV32-MEDIUM
+; RUN: llc < %s -mtriple=riscv32 -global-isel -relocation-model=pic \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=RV32-PIC
+; RUN: llc < %s -mtriple=riscv64 -global-isel -code-model=small \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=RV64-SMALL
+; RUN: llc < %s -mtriple=riscv64 -global-isel -code-model=medium \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=RV64-MEDIUM
+; RUN: llc < %s -mtriple=riscv64 -global-isel -relocation-model=pic \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=RV64-PIC
+
+define void @constpool_f32(ptr %p) {
+; RV32-SMALL-LABEL: constpool_f32:
+; RV32-SMALL: # %bb.0:
+; RV32-SMALL-NEXT: lui a1, %hi(.LCPI0_0)
+; RV32-SMALL-NEXT: lw a1, %lo(.LCPI0_0)(a1)
+; RV32-SMALL-NEXT: sw a1, 0(a0)
+; RV32-SMALL-NEXT: ret
+;
+; RV32-MEDIUM-LABEL: constpool_f32:
+; RV32-MEDIUM: # %bb.0:
+; RV32-MEDIUM-NEXT: .Lpcrel_hi0:
+; RV32-MEDIUM-NEXT: auipc a1, %pcrel_hi(.LCPI0_0)
+; RV32-MEDIUM-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi0)(a1)
+; RV32-MEDIUM-NEXT: sw a1, 0(a0)
+; RV32-MEDIUM-NEXT: ret
+;
+; RV32-PIC-LABEL: constpool_f32:
+; RV32-PIC: # %bb.0:
+; RV32-PIC-NEXT: .Lpcrel_hi0:
+; RV32-PIC-NEXT: auipc a1, %pcrel_hi(.LCPI0_0)
+; RV32-PIC-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi0)(a1)
+; RV32-PIC-NEXT: sw a1, 0(a0)
+; RV32-PIC-NEXT: ret
+;
+; RV64-SMALL-LABEL: constpool_f32:
+; RV64-SMALL: # %bb.0:
+; RV64-SMALL-NEXT: lui a1, %hi(.LCPI0_0)
+; RV64-SMALL-NEXT: lw a1, %lo(.LCPI0_0)(a1)
+; RV64-SMALL-NEXT: sw a1, 0(a0)
+; RV64-SMALL-NEXT: ret
+;
+; RV64-MEDIUM-LABEL: constpool_f32:
+; RV64-MEDIUM: # %bb.0:
+; RV64-MEDIUM-NEXT: .Lpcrel_hi0:
+; RV64-MEDIUM-NEXT: auipc a1, %pcrel_hi(.LCPI0_0)
+; RV64-MEDIUM-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi0)(a1)
+; RV64-MEDIUM-NEXT: sw a1, 0(a0)
+; RV64-MEDIUM-NEXT: ret
+;
+; RV64-PIC-LABEL: constpool_f32:
+; RV64-PIC: # %bb.0:
+; RV64-PIC-NEXT: .Lpcrel_hi0:
+; RV64-PIC-NEXT: auipc a1, %pcrel_hi(.LCPI0_0)
+; RV64-PIC-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi0)(a1)
+; RV64-PIC-NEXT: sw a1, 0(a0)
+; RV64-PIC-NEXT: ret
+ store float 1.0, ptr %p
+ ret void
+}
+
+define void @constpool_f64(ptr %p) {
+; RV32-SMALL-LABEL: constpool_f64:
+; RV32-SMALL: # %bb.0:
+; RV32-SMALL-NEXT: lui a1, %hi(.LCPI1_0)
+; RV32-SMALL-NEXT: addi a1, a1, %lo(.LCPI1_0)
+; RV32-SMALL-NEXT: lw a2, 0(a1)
+; RV32-SMALL-NEXT: lw a1, 4(a1)
+; RV32-SMALL-NEXT: sw a2, 0(a0)
+; RV32-SMALL-NEXT: sw a1, 4(a0)
+; RV32-SMALL-NEXT: ret
+;
+; RV32-MEDIUM-LABEL: constpool_f64:
+; RV32-MEDIUM: # %bb.0:
+; RV32-MEDIUM-NEXT: .Lpcrel_hi1:
+; RV32-MEDIUM-NEXT: auipc a1, %pcrel_hi(.LCPI1_0)
+; RV32-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.Lpcrel_hi1)
+; RV32-MEDIUM-NEXT: lw a2, 0(a1)
+; RV32-MEDIUM-NEXT: lw a1, 4(a1)
+; RV32-MEDIUM-NEXT: sw a2, 0(a0)
+; RV32-MEDIUM-NEXT: sw a1, 4(a0)
+; RV32-MEDIUM-NEXT: ret
+;
+; RV32-PIC-LABEL: constpool_f64:
+; RV32-PIC: # %bb.0:
+; RV32-PIC-NEXT: .Lpcrel_hi1:
+; RV32-PIC-NEXT: auipc a1, %pcrel_hi(.LCPI1_0)
+; RV32-PIC-NEXT: addi a1, a1, %pcrel_lo(.Lpcrel_hi1)
+; RV32-PIC-NEXT: lw a2, 0(a1)
+; RV32-PIC-NEXT: lw a1, 4(a1)
+; RV32-PIC-NEXT: sw a2, 0(a0)
+; RV32-PIC-NEXT: sw a1, 4(a0)
+; RV32-PIC-NEXT: ret
+;
+; RV64-SMALL-LABEL: constpool_f64:
+; RV64-SMALL: # %bb.0:
+; RV64-SMALL-NEXT: lui a1, %hi(.LCPI1_0)
+; RV64-SMALL-NEXT: ld a1, %lo(.LCPI1_0)(a1)
+; RV64-SMALL-NEXT: sd a1, 0(a0)
+; RV64-SMALL-NEXT: ret
+;
+; RV64-MEDIUM-LABEL: constpool_f64:
+; RV64-MEDIUM: # %bb.0:
+; RV64-MEDIUM-NEXT: .Lpcrel_hi1:
+; RV64-MEDIUM-NEXT: auipc a1, %pcrel_hi(.LCPI1_0)
+; RV64-MEDIUM-NEXT: ld a1, %pcrel_lo(.Lpcrel_hi1)(a1)
+; RV64-MEDIUM-NEXT: sd a1, 0(a0)
+; RV64-MEDIUM-NEXT: ret
+;
+; RV64-PIC-LABEL: constpool_f64:
+; RV64-PIC: # %bb.0:
+; RV64-PIC-NEXT: .Lpcrel_hi1:
+; RV64-PIC-NEXT: auipc a1, %pcrel_hi(.LCPI1_0)
+; RV64-PIC-NEXT: ld a1, %pcrel_lo(.Lpcrel_hi1)(a1)
+; RV64-PIC-NEXT: sd a1, 0(a0)
+; RV64-PIC-NEXT: ret
+ store double 1.0, ptr %p
+ ret void
+}
>From 222f6c438e8607fea087ed660e336ee3699983ab Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 27 Nov 2023 20:42:39 -0800
Subject: [PATCH 2/2] fixup! reduce code duplication
---
llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 8f8a4cccc705f73..aec7de329eae35c 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -531,7 +531,6 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
GV->hasExternalWeakLinkage());
}
case TargetOpcode::G_JUMP_TABLE:
- return selectAddr(MI, MIB, MRI);
case TargetOpcode::G_CONSTANT_POOL:
return selectAddr(MI, MIB, MRI);
case TargetOpcode::G_BRCOND: {
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