[llvm] a3b7b2d - [X86][CodeGen] Not compress EVEX into VEX when R16-R31 is used (#73604)

[via llvm-commits]

Author: Shengchen Kan
Date: 2023-11-28T11:40:48+08:00
New Revision: a3b7b2d6354f622372ce6967e082869979c25ed8

URL: https://github.com/llvm/llvm-project/commit/a3b7b2d6354f622372ce6967e082869979c25ed8
DIFF: https://github.com/llvm/llvm-project/commit/a3b7b2d6354f622372ce6967e082869979c25ed8.diff

LOG: [X86][CodeGen] Not compress EVEX into VEX when R16-R31 is used (#73604)

b/c VEX prefix can not encode R16-R31.

Added: 
    llvm/test/CodeGen/X86/apx/evex-to-vex.ll

Modified: 
    llvm/lib/Target/X86/X86EvexToVex.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86EvexToVex.cpp b/llvm/lib/Target/X86/X86EvexToVex.cpp
index 88366558562c51e..fda6c15fed34db7 100644
--- a/llvm/lib/Target/X86/X86EvexToVex.cpp
+++ b/llvm/lib/Target/X86/X86EvexToVex.cpp
@@ -125,6 +125,10 @@ static bool usesExtendedRegister(const MachineInstr &MI) {
     if (Reg >= X86::YMM16 && Reg <= X86::YMM31)
       return true;
 
+    // Check for GPR with indexes between 16 - 31.
+    if (X86II::isApxExtendedReg(Reg))
+      return true;
+
     return false;
   };
 

diff  --git a/llvm/test/CodeGen/X86/apx/evex-to-vex.ll b/llvm/test/CodeGen/X86/apx/evex-to-vex.ll
new file mode 100644
index 000000000000000..f70c50eb468c3f0
--- /dev/null
+++ b/llvm/test/CodeGen/X86/apx/evex-to-vex.ll
@@ -0,0 +1,14 @@
+; Check EVEX is not compressed into VEX when egpr is used.
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl,+egpr -show-mc-encoding | FileCheck %s
+
+define void @test_x86_vcvtps2ph_256_m(ptr nocapture %d, <8 x float> %a) nounwind {
+; CHECK:    vcvtps2ph $3, %ymm0, (%r16) # encoding: [0x62,0xfb,0x7d,0x28,0x1d,0x00,0x03]
+entry:
+  %0 = load i32, ptr %d, align 4
+  call void asm sideeffect "", "~{eax},~{ebx},~{ecx},~{edx},~{edi},~{esi},~{ebp},~{esp},~{r8d},~{r9d},~{r10d},~{r11d},~{r12d},~{r13d},~{r14d},~{r15d}"()
+  %1 = tail call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %a, i32 3)
+  store <8 x i16> %1, ptr %d, align 16
+  ret void
+}
+
+declare <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float>, i32) nounwind readonly