[llvm] [RISCV] Split build_vector into vreg sized pieces when exact VLEN is known (PR #73606)

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git-clang-format --diff 5d59e97e883445f36e99d4b9600330ac4a631565 61d352055402689dfa22d818ba830ff9ec7642a6 -- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 2107996e10..a7119ab159 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -3762,8 +3762,7 @@ static SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
   // register in the register group.
   const unsigned MinVLen = Subtarget.getRealMinVLen();
   const unsigned MaxVLen = Subtarget.getRealMaxVLen();
-  if (MinVLen == MaxVLen &&
-      VT.getSizeInBits().getKnownMinValue() > MinVLen) {
+  if (MinVLen == MaxVLen && VT.getSizeInBits().getKnownMinValue() > MinVLen) {
     MVT ElemVT = VT.getVectorElementType();
     unsigned ElemSize = ElemVT.getSizeInBits().getKnownMinValue();
     unsigned ElemsPerVReg = MinVLen / ElemSize;
@@ -3782,10 +3781,12 @@ static SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
     SDValue Vec = DAG.getUNDEF(ContainerVT);
     for (unsigned i = 0; i < VT.getVectorNumElements(); i += ElemsPerVReg) {
       auto OneVRegOfOps = ArrayRef(BuildVectorOps).slice(i, ElemsPerVReg);
-      SDValue SubBV = DAG.getNode(ISD::BUILD_VECTOR, DL, OneRegVT, OneVRegOfOps);
+      SDValue SubBV =
+          DAG.getNode(ISD::BUILD_VECTOR, DL, OneRegVT, OneVRegOfOps);
       SubBV = convertToScalableVector(M1VT, SubBV, DAG, Subtarget);
-      Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ContainerVT, Vec, SubBV,
-                        DAG.getIntPtrConstant((i / ElemsPerVReg) * NumOpElts, DL));
+      Vec = DAG.getNode(
+          ISD::INSERT_SUBVECTOR, DL, ContainerVT, Vec, SubBV,
+          DAG.getIntPtrConstant((i / ElemsPerVReg) * NumOpElts, DL));
     }
     return convertFromScalableVector(VT, Vec, DAG, Subtarget);
   }

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https://github.com/llvm/llvm-project/pull/73606