[llvm] [RISCV][GISEL] legalize, regbankselect, and instruction-select for G_… (PR #73061)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 27 17:10:59 PST 2023
================
@@ -353,6 +353,34 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
OpdsMapping[2] = OpdsMapping[3] = getFPValueMapping(Size);
break;
}
+ case TargetOpcode::G_MERGE_VALUES: {
+ // Use FPR64 for s64 merge on rv32.
+ assert(MI.getNumOperands() == 3 && "Unsupported G_MERGE_VALUES");
+ LLT Ty = MRI.getType(MI.getOperand(0).getReg());
+ if (GPRSize == 32 && Ty.getSizeInBits() == 64) {
+ assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD());
+ // FIXME: OpdsMapping[0, 1] should probably visit their uses to determine
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topperc wrote:
What opcode would we use for that case?
https://github.com/llvm/llvm-project/pull/73061
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