[llvm] [RISCV][GISEL] legalize, regbankselect, and instruction-select G_PTRMASK (PR #73062)
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 27 15:01:50 PST 2023
https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/73062
>From b9000ab9b403876bea930d5b49e7b53ac7fb9243 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Fri, 17 Nov 2023 07:37:47 -0800
Subject: [PATCH 1/4] [RISCV][GISEL] Legalize G_PTRMASK
G_PTRMASK is custom legalized by using G_PTRTOINT on the pointer, using a
G_AND to calculate the mask, and converted back to pointer using G_PTRTOINT.
---
.../Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 23 ++++++++++++++++++
.../Target/RISCV/GISel/RISCVLegalizerInfo.h | 3 +++
.../legalizer/legalize-ptrmask-rv32.mir | 24 +++++++++++++++++++
.../legalizer/legalize-ptrmask-rv64.mir | 24 +++++++++++++++++++
4 files changed, 74 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrmask-rv32.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrmask-rv64.mir
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 9eb5812e024b915..1c1c4ee6a9aed3a 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -147,6 +147,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
getActionDefinitionsBuilder(G_PTR_ADD).legalFor({{p0, sXLen}});
+ getActionDefinitionsBuilder(G_PTRMASK).customFor({{p0, sXLen}});
+
getActionDefinitionsBuilder(G_PTRTOINT)
.legalFor({{sXLen, p0}})
.clampScalar(0, sXLen, sXLen);
@@ -288,6 +290,25 @@ bool RISCVLegalizerInfo::legalizeShlAshrLshr(
return true;
}
+bool RISCVLegalizerInfo::legalizePtrMask(MachineInstr &MI,
+ MachineIRBuilder &MIRBuilder,
+ GISelChangeObserver &Observer) const {
+ assert(MI.getOpcode() == TargetOpcode::G_PTRMASK);
+
+ MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
+ Register Tmp1 =
+ MRI.createGenericVirtualRegister(MRI.getType(MI.getOperand(2).getReg()));
+ Register Tmp2 =
+ MRI.createGenericVirtualRegister(MRI.getType(MI.getOperand(2).getReg()));
+ MIRBuilder.buildPtrToInt(Tmp1, MI.getOperand(1).getReg());
+ MIRBuilder.buildAnd(Tmp2, Tmp1, MI.getOperand(2).getReg());
+ MIRBuilder.buildIntToPtr(MI.getOperand(0).getReg(), Tmp2);
+
+ Observer.erasingInstr(MI);
+ MI.eraseFromParent();
+ return true;
+}
+
bool RISCVLegalizerInfo::legalizeCustom(LegalizerHelper &Helper,
MachineInstr &MI) const {
MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
@@ -309,6 +330,8 @@ bool RISCVLegalizerInfo::legalizeCustom(LegalizerHelper &Helper,
return Helper.lower(MI, 0, /* Unused hint type */ LLT()) ==
LegalizerHelper::Legalized;
}
+ case TargetOpcode::G_PTRMASK:
+ return legalizePtrMask(MI, MIRBuilder, Observer);
}
llvm_unreachable("expected switch to return");
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
index f39d3a130d85063..ff2be0622023795 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
@@ -31,6 +31,9 @@ class RISCVLegalizerInfo : public LegalizerInfo {
private:
bool legalizeShlAshrLshr(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
GISelChangeObserver &Observer) const;
+
+ bool legalizePtrMask(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
+ GISelChangeObserver &Observer) const;
};
} // end namespace llvm
#endif
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrmask-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrmask-rv32.mir
new file mode 100644
index 000000000000000..af91461040047f8
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrmask-rv32.mir
@@ -0,0 +1,24 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: ptrmask_p0_s32
+body: |
+ bb.0:
+ liveins: $x10, $x11
+ ; CHECK-LABEL: name: ptrmask_p0_s32
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[PTRTOINT]], [[COPY1]]
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[INTTOPTR]](p0)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s32) = COPY $x11
+ %2:_(p0) = G_PTRMASK %0(p0), %1(s32)
+ $x10 = COPY %2(p0)
+ PseudoRET implicit $x10
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrmask-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrmask-rv64.mir
new file mode 100644
index 000000000000000..b7223c1e2ca2ea6
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrmask-rv64.mir
@@ -0,0 +1,24 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: ptrmask_p0_s64
+body: |
+ bb.0:
+ liveins: $x10, $x11
+ ; CHECK-LABEL: name: ptrmask_p0_s64
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[PTRTOINT]], [[COPY1]]
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[INTTOPTR]](p0)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s64) = COPY $x11
+ %2:_(p0) = G_PTRMASK %0(p0), %1(s64)
+ $x10 = COPY %2(p0)
+ PseudoRET implicit $x10
+...
>From 31b12b04fcce32d2583236fa72f8ca52475849bc Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Wed, 22 Nov 2023 08:08:49 -0800
Subject: [PATCH 2/4] !fixup move from custom legalization to
LegalizerHelper::lower
---
.../llvm/CodeGen/GlobalISel/LegalizerHelper.h | 1 +
.../CodeGen/GlobalISel/LegalizerHelper.cpp | 19 +++++++++++++++
.../Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 24 +------------------
.../Target/RISCV/GISel/RISCVLegalizerInfo.h | 3 ---
4 files changed, 21 insertions(+), 26 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
index 86d3cb2bedb95b6..4b528e7d7d30375 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
@@ -430,6 +430,7 @@ class LegalizerHelper {
LegalizeResult lowerVectorReduction(MachineInstr &MI);
LegalizeResult lowerMemcpyInline(MachineInstr &MI);
LegalizeResult lowerMemCpyFamily(MachineInstr &MI, unsigned MaxLen = 0);
+ LegalizeResult lowerPtrMask(MachineInstr &MI);
};
/// Helper function that creates a libcall to the given \p Name using the given
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index dd5577d47f97764..fd5cd7b7ac64cbd 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -3780,6 +3780,8 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
return lowerTRUNC(MI);
GISEL_VECREDUCE_CASES_NONSEQ
return lowerVectorReduction(MI);
+ case G_PTRMASK:
+ return lowerPtrMask(MI);
}
}
@@ -8405,3 +8407,20 @@ LegalizerHelper::lowerMemCpyFamily(MachineInstr &MI, unsigned MaxLen) {
return lowerMemset(MI, Dst, Src, KnownLen, DstAlign, IsVolatile);
return UnableToLegalize;
}
+
+LegalizerHelper::LegalizeResult
+LegalizerHelper::lowerPtrMask(MachineInstr &MI) {
+ assert(MI.getOpcode() == TargetOpcode::G_PTRMASK);
+
+ MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
+ Register Tmp1 =
+ MRI.createGenericVirtualRegister(MRI.getType(MI.getOperand(2).getReg()));
+ Register Tmp2 =
+ MRI.createGenericVirtualRegister(MRI.getType(MI.getOperand(2).getReg()));
+ MIRBuilder.buildPtrToInt(Tmp1, MI.getOperand(1).getReg());
+ MIRBuilder.buildAnd(Tmp2, Tmp1, MI.getOperand(2).getReg());
+ MIRBuilder.buildIntToPtr(MI.getOperand(0).getReg(), Tmp2);
+
+ MI.eraseFromParent();
+ return Legalized;
+}
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 1c1c4ee6a9aed3a..80d41f26ef64ad5 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -147,7 +147,7 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
getActionDefinitionsBuilder(G_PTR_ADD).legalFor({{p0, sXLen}});
- getActionDefinitionsBuilder(G_PTRMASK).customFor({{p0, sXLen}});
+ getActionDefinitionsBuilder(G_PTRMASK).lowerFor({{p0, sXLen}});
getActionDefinitionsBuilder(G_PTRTOINT)
.legalFor({{sXLen, p0}})
@@ -290,25 +290,6 @@ bool RISCVLegalizerInfo::legalizeShlAshrLshr(
return true;
}
-bool RISCVLegalizerInfo::legalizePtrMask(MachineInstr &MI,
- MachineIRBuilder &MIRBuilder,
- GISelChangeObserver &Observer) const {
- assert(MI.getOpcode() == TargetOpcode::G_PTRMASK);
-
- MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
- Register Tmp1 =
- MRI.createGenericVirtualRegister(MRI.getType(MI.getOperand(2).getReg()));
- Register Tmp2 =
- MRI.createGenericVirtualRegister(MRI.getType(MI.getOperand(2).getReg()));
- MIRBuilder.buildPtrToInt(Tmp1, MI.getOperand(1).getReg());
- MIRBuilder.buildAnd(Tmp2, Tmp1, MI.getOperand(2).getReg());
- MIRBuilder.buildIntToPtr(MI.getOperand(0).getReg(), Tmp2);
-
- Observer.erasingInstr(MI);
- MI.eraseFromParent();
- return true;
-}
-
bool RISCVLegalizerInfo::legalizeCustom(LegalizerHelper &Helper,
MachineInstr &MI) const {
MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
@@ -330,9 +311,6 @@ bool RISCVLegalizerInfo::legalizeCustom(LegalizerHelper &Helper,
return Helper.lower(MI, 0, /* Unused hint type */ LLT()) ==
LegalizerHelper::Legalized;
}
- case TargetOpcode::G_PTRMASK:
- return legalizePtrMask(MI, MIRBuilder, Observer);
}
-
llvm_unreachable("expected switch to return");
}
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
index ff2be0622023795..f39d3a130d85063 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
@@ -31,9 +31,6 @@ class RISCVLegalizerInfo : public LegalizerInfo {
private:
bool legalizeShlAshrLshr(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
GISelChangeObserver &Observer) const;
-
- bool legalizePtrMask(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
- GISelChangeObserver &Observer) const;
};
} // end namespace llvm
#endif
>From 9b767b19576fc8e2fb043a6e6887f7bc3fbf129e Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Mon, 27 Nov 2023 14:47:59 -0800
Subject: [PATCH 3/4] !fixup move to instruction-selection
---
.../llvm/CodeGen/GlobalISel/LegalizerHelper.h | 1 -
.../CodeGen/GlobalISel/LegalizerHelper.cpp | 19 --------------
.../RISCV/GISel/RISCVInstructionSelector.cpp | 7 ++++++
.../Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 4 +--
.../instruction-select/ptrmask-rv32.mir | 25 +++++++++++++++++++
.../instruction-select/ptrmask-rv64.mir | 25 +++++++++++++++++++
.../legalizer/legalize-ptrmask-rv32.mir | 6 ++---
.../legalizer/legalize-ptrmask-rv64.mir | 6 ++---
.../GlobalISel/regbankselect/ptrmask-rv32.mir | 24 ++++++++++++++++++
.../GlobalISel/regbankselect/ptrmask-rv64.mir | 24 ++++++++++++++++++
10 files changed, 110 insertions(+), 31 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptrmask-rv32.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptrmask-rv64.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv32.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv64.mir
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
index 4b528e7d7d30375..86d3cb2bedb95b6 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
@@ -430,7 +430,6 @@ class LegalizerHelper {
LegalizeResult lowerVectorReduction(MachineInstr &MI);
LegalizeResult lowerMemcpyInline(MachineInstr &MI);
LegalizeResult lowerMemCpyFamily(MachineInstr &MI, unsigned MaxLen = 0);
- LegalizeResult lowerPtrMask(MachineInstr &MI);
};
/// Helper function that creates a libcall to the given \p Name using the given
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index fd5cd7b7ac64cbd..dd5577d47f97764 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -3780,8 +3780,6 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
return lowerTRUNC(MI);
GISEL_VECREDUCE_CASES_NONSEQ
return lowerVectorReduction(MI);
- case G_PTRMASK:
- return lowerPtrMask(MI);
}
}
@@ -8407,20 +8405,3 @@ LegalizerHelper::lowerMemCpyFamily(MachineInstr &MI, unsigned MaxLen) {
return lowerMemset(MI, Dst, Src, KnownLen, DstAlign, IsVolatile);
return UnableToLegalize;
}
-
-LegalizerHelper::LegalizeResult
-LegalizerHelper::lowerPtrMask(MachineInstr &MI) {
- assert(MI.getOpcode() == TargetOpcode::G_PTRMASK);
-
- MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
- Register Tmp1 =
- MRI.createGenericVirtualRegister(MRI.getType(MI.getOperand(2).getReg()));
- Register Tmp2 =
- MRI.createGenericVirtualRegister(MRI.getType(MI.getOperand(2).getReg()));
- MIRBuilder.buildPtrToInt(Tmp1, MI.getOperand(1).getReg());
- MIRBuilder.buildAnd(Tmp2, Tmp1, MI.getOperand(2).getReg());
- MIRBuilder.buildIntToPtr(MI.getOperand(0).getReg(), Tmp2);
-
- MI.eraseFromParent();
- return Legalized;
-}
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 3c72269d1e00c2f..3857861521f7a30 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -595,6 +595,13 @@ void RISCVInstructionSelector::preISelLower(MachineInstr &MI,
MRI.setType(DstReg, sXLen);
break;
}
+ case TargetOpcode::G_PTRMASK: {
+ Register DstReg = MI.getOperand(0).getReg();
+ const LLT sXLen = LLT::scalar(STI.getXLen());
+ replacePtrWithInt(MI.getOperand(1), MIB, MRI);
+ MI.setDesc(TII.get(TargetOpcode::G_AND));
+ MRI.setType(DstReg, sXLen);
+ }
}
}
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 80d41f26ef64ad5..f8e0d08ad803001 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -145,9 +145,7 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
LoadStoreActions.clampScalar(0, s32, sXLen).lower();
ExtLoadActions.widenScalarToNextPow2(0).clampScalar(0, s32, sXLen).lower();
- getActionDefinitionsBuilder(G_PTR_ADD).legalFor({{p0, sXLen}});
-
- getActionDefinitionsBuilder(G_PTRMASK).lowerFor({{p0, sXLen}});
+ getActionDefinitionsBuilder({G_PTR_ADD, G_PTRMASK}).legalFor({{p0, sXLen}});
getActionDefinitionsBuilder(G_PTRTOINT)
.legalFor({{sXLen, p0}})
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptrmask-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptrmask-rv32.mir
new file mode 100644
index 000000000000000..0e76647a4b91f58
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptrmask-rv32.mir
@@ -0,0 +1,25 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: ptrmask_p0_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x10, $x11
+ ; CHECK-LABEL: name: ptrmask_p0_s32
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:gpr = AND [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $x10 = COPY [[AND]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(p0) = COPY $x10
+ %1:gprb(s32) = COPY $x11
+ %2:gprb(p0) = G_PTRMASK %0(p0), %1(s32)
+ $x10 = COPY %2(p0)
+ PseudoRET implicit $x10
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptrmask-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptrmask-rv64.mir
new file mode 100644
index 000000000000000..02631c6f3be0671
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptrmask-rv64.mir
@@ -0,0 +1,25 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: ptrmask_p0_s64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x10, $x11
+ ; CHECK-LABEL: name: ptrmask_p0_s64
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:gpr = AND [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $x10 = COPY [[AND]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(p0) = COPY $x10
+ %1:gprb(s64) = COPY $x11
+ %2:gprb(p0) = G_PTRMASK %0(p0), %1(s64)
+ $x10 = COPY %2(p0)
+ PseudoRET implicit $x10
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrmask-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrmask-rv32.mir
index af91461040047f8..dd645b0bc12eeef 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrmask-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrmask-rv32.mir
@@ -11,10 +11,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p0)
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[PTRTOINT]], [[COPY1]]
- ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND]](s32)
- ; CHECK-NEXT: $x10 = COPY [[INTTOPTR]](p0)
+ ; CHECK-NEXT: [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[COPY]], [[COPY1]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[PTRMASK]](p0)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(p0) = COPY $x10
%1:_(s32) = COPY $x11
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrmask-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrmask-rv64.mir
index b7223c1e2ca2ea6..eced48ff155006f 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrmask-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrmask-rv64.mir
@@ -11,10 +11,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[PTRTOINT]], [[COPY1]]
- ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND]](s64)
- ; CHECK-NEXT: $x10 = COPY [[INTTOPTR]](p0)
+ ; CHECK-NEXT: [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[COPY]], [[COPY1]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[PTRMASK]](p0)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(p0) = COPY $x10
%1:_(s64) = COPY $x11
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv32.mir
new file mode 100644
index 000000000000000..089dd7ada0a9bc9
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv32.mir
@@ -0,0 +1,24 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: ptrmask_p0_s32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x10, $x11
+ ; CHECK-LABEL: name: ptrmask_p0_s32
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+ ; CHECK-NEXT: [[PTRMASK:%[0-9]+]]:gprb(p0) = G_PTRMASK [[COPY]], [[COPY1]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[PTRMASK]](p0)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s32) = COPY $x11
+ %2:_(p0) = G_PTRMASK %0(p0), %1(s32)
+ $x10 = COPY %2(p0)
+ PseudoRET implicit $x10
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv64.mir
new file mode 100644
index 000000000000000..e0e765e368d1de8
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv64.mir
@@ -0,0 +1,24 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: ptrmask_p0_s64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x10, $x11
+ ; CHECK-LABEL: name: ptrmask_p0_s64
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+ ; CHECK-NEXT: [[PTRMASK:%[0-9]+]]:gprb(p0) = G_PTRMASK [[COPY]], [[COPY1]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[PTRMASK]](p0)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s64) = COPY $x11
+ %2:_(p0) = G_PTRMASK %0(p0), %1(s64)
+ $x10 = COPY %2(p0)
+ PseudoRET implicit $x10
+...
>From 3d2e4f29904b6b6ba90662f3c1cfb9e6d8c76163 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Mon, 27 Nov 2023 15:00:39 -0800
Subject: [PATCH 4/4] !fixup don't delete blank line
---
llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index f8e0d08ad803001..6442c67b802f1f7 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -310,5 +310,6 @@ bool RISCVLegalizerInfo::legalizeCustom(LegalizerHelper &Helper,
LegalizerHelper::Legalized;
}
}
+
llvm_unreachable("expected switch to return");
}
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