[llvm] [RISCV][GISEL] Select G_IMPLICIT_DEF (PR #73060)

Maksim Levental via llvm-commits llvm-commits at lists.llvm.org
Mon Nov 27 13:58:14 PST 2023


https://github.com/makslevental updated https://github.com/llvm/llvm-project/pull/73060

>From 82ad45e7eeb753d5d50540281d2be1a3be16a3b7 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Fri, 17 Nov 2023 08:58:16 -0800
Subject: [PATCH 1/2] [RISCV][GISEL] Select G_IMPLICIT_DEF

This is similiar to the selection of G_IMPLICIT_DEF in AArch64. Register bank
selection needs to be implemented in a future patch. It is not so
straight forward since the register bank information is ambigious on its
own and depends on its uses.
---
 .../RISCV/GISel/RISCVInstructionSelector.cpp  | 23 ++++++
 .../instruction-select/implicit-def32.mir     | 75 +++++++++++++++++++
 .../instruction-select/implicit-def64.mir     | 75 +++++++++++++++++++
 3 files changed, 173 insertions(+)
 create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def32.mir
 create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def64.mir

diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 3c72269d1e00c2f..5999fb4840b9ea0 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -62,6 +62,8 @@ class RISCVInstructionSelector : public InstructionSelector {
 
   // Custom selection methods
   bool selectCopy(MachineInstr &MI, MachineRegisterInfo &MRI) const;
+  bool selectImplicitDef(MachineInstr &MI, MachineIRBuilder &MIB,
+                         MachineRegisterInfo &MRI) const;
   bool materializeImm(Register Reg, int64_t Imm, MachineIRBuilder &MIB) const;
   bool selectGlobalValue(MachineInstr &MI, MachineIRBuilder &MIB,
                          MachineRegisterInfo &MRI) const;
@@ -564,6 +566,8 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
     return selectSelect(MI, MIB, MRI);
   case TargetOpcode::G_FCMP:
     return selectFPCompare(MI, MIB, MRI);
+  case TargetOpcode::G_IMPLICIT_DEF:
+    return selectImplicitDef(MI, MIB, MRI);
   default:
     return false;
   }
@@ -677,6 +681,25 @@ bool RISCVInstructionSelector::selectCopy(MachineInstr &MI,
   return true;
 }
 
+bool RISCVInstructionSelector::selectImplicitDef(
+    MachineInstr &MI, MachineIRBuilder &MIB, MachineRegisterInfo &MRI) const {
+  assert(MI.getOpcode() == TargetOpcode::G_IMPLICIT_DEF);
+
+  const Register DstReg = MI.getOperand(0).getReg();
+  const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(
+      MRI.getType(DstReg), *RBI.getRegBank(DstReg, MRI, TRI));
+
+  assert(DstRC &&
+         "Register class not available for LLT, register bank combination");
+
+  if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
+    LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(MI.getOpcode())
+                      << " operand\n");
+  }
+  MI.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF));
+  return true;
+}
+
 bool RISCVInstructionSelector::materializeImm(Register DstReg, int64_t Imm,
                                               MachineIRBuilder &MIB) const {
   MachineRegisterInfo &MRI = *MIB.getMRI();
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def32.mir
new file mode 100644
index 000000000000000..10a5246a99d2b4d
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def32.mir
@@ -0,0 +1,75 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+f -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
+# RUN: | FileCheck -check-prefix=RV32F %s
+
+---
+name:            implicit_def_gpr
+legalized:       true
+regBankSelected: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+
+body:             |
+  bb.0:
+    ; RV32F-LABEL: name: implicit_def_gpr
+    ; RV32F: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF
+    ; RV32F-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[DEF]], [[DEF]]
+    ; RV32F-NEXT: $x10 = COPY [[ADD]]
+    %0(s32) = G_IMPLICIT_DEF
+    %1(s32) = G_ADD %0, %0
+    $x10 = COPY %1(s32)
+...
+---
+name:            implicit_def_copy_gpr
+legalized:       true
+regBankSelected: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+
+body:             |
+  bb.0:
+    ; RV32F-LABEL: name: implicit_def_copy_gpr
+    ; RV32F: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF
+    ; RV32F-NEXT: $x10 = COPY [[DEF]]
+    %0(s32) = G_IMPLICIT_DEF
+    %1(s32) = COPY %0(s32)
+    $x10 = COPY %1(s32)
+...
+
+---
+name:            implicit_def_fpr
+legalized:       true
+regBankSelected: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+
+body:             |
+  bb.0:
+    ; RV32F-LABEL: name: implicit_def_fpr
+    ; RV32F: [[DEF:%[0-9]+]]:fpr32 = IMPLICIT_DEF
+    ; RV32F-NEXT: [[FADD_S:%[0-9]+]]:fpr32 = nofpexcept FADD_S [[DEF]], [[DEF]], 7
+    ; RV32F-NEXT: $f10_f = COPY [[FADD_S]]
+    %0(s32) = G_IMPLICIT_DEF
+    %1(s32) = G_FADD %0, %0
+    $f10_f = COPY %1(s32)
+...
+---
+name:            implicit_def_copy_fpr
+legalized:       true
+regBankSelected: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+
+body:             |
+  bb.0:
+    ; RV32F-LABEL: name: implicit_def_copy_fpr
+    ; RV32F: [[DEF:%[0-9]+]]:fpr32 = IMPLICIT_DEF
+    ; RV32F-NEXT: $f10_f = COPY [[DEF]]
+    %0(s32) = G_IMPLICIT_DEF
+    %1(s32) = COPY %0(s32)
+    $f10_f = COPY %1(s32)
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def64.mir
new file mode 100644
index 000000000000000..1aafca8374ff908
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def64.mir
@@ -0,0 +1,75 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
+# RUN: | FileCheck -check-prefix=RV64D %s
+
+---
+name:            implicit_def_gpr
+legalized:       true
+regBankSelected: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+
+body:             |
+  bb.0:
+    ; RV64D-LABEL: name: implicit_def_gpr
+    ; RV64D: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF
+    ; RV64D-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[DEF]], [[DEF]]
+    ; RV64D-NEXT: $x10 = COPY [[ADD]]
+    %0(s64) = G_IMPLICIT_DEF
+    %1(s64) = G_ADD %0, %0
+    $x10 = COPY %1(s64)
+...
+---
+name:            implicit_def_copy_gpr
+legalized:       true
+regBankSelected: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+
+body:             |
+  bb.0:
+    ; RV64D-LABEL: name: implicit_def_copy_gpr
+    ; RV64D: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF
+    ; RV64D-NEXT: $x10 = COPY [[DEF]]
+    %0(s64) = G_IMPLICIT_DEF
+    %1(s64) = COPY %0(s64)
+    $x10 = COPY %1(s64)
+...
+
+---
+name:            implicit_def_fpr
+legalized:       true
+regBankSelected: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+
+body:             |
+  bb.0:
+    ; RV64D-LABEL: name: implicit_def_fpr
+    ; RV64D: [[DEF:%[0-9]+]]:fpr64 = IMPLICIT_DEF
+    ; RV64D-NEXT: [[FADD_D:%[0-9]+]]:fpr64 = nofpexcept FADD_D [[DEF]], [[DEF]], 7
+    ; RV64D-NEXT: $f10_d = COPY [[FADD_D]]
+    %0(s64) = G_IMPLICIT_DEF
+    %1(s64) = G_FADD %0, %0
+    $f10_d = COPY %1(s64)
+...
+---
+name:            implicit_def_copy_fpr
+legalized:       true
+regBankSelected: true
+registers:
+  - { id: 0, class: fprb }
+  - { id: 1, class: fprb }
+
+body:             |
+  bb.0:
+    ; RV64D-LABEL: name: implicit_def_copy_fpr
+    ; RV64D: [[DEF:%[0-9]+]]:fpr64 = IMPLICIT_DEF
+    ; RV64D-NEXT: $f10_d = COPY [[DEF]]
+    %0(s64) = G_IMPLICIT_DEF
+    %1(s64) = COPY %0(s64)
+    $f10_d = COPY %1(s64)
+...

>From 0b24758f4f6738d6c064028dfb880683dcf5f6df Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Mon, 27 Nov 2023 13:57:55 -0800
Subject: [PATCH 2/2] !fixup fix test naming conventions

---
 .../{implicit-def32.mir => implicit-def-rv32.mir}                 | 0
 .../{implicit-def64.mir => implicit-def-rv64.mir}                 | 0
 2 files changed, 0 insertions(+), 0 deletions(-)
 rename llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/{implicit-def32.mir => implicit-def-rv32.mir} (100%)
 rename llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/{implicit-def64.mir => implicit-def-rv64.mir} (100%)

diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def-rv32.mir
similarity index 100%
rename from llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def32.mir
rename to llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def-rv32.mir
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def-rv64.mir
similarity index 100%
rename from llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def64.mir
rename to llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def-rv64.mir



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