[llvm] [RISCV][GISel] Select trap and debugtrap. (PR #73171)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 27 13:38:26 PST 2023
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/73171
>From c9929921aa0c8424ec3864182bb65d986359a3c9 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Wed, 22 Nov 2023 13:24:30 -0800
Subject: [PATCH 1/4] [RISCV][GISel] Select trap and debugtrap.
---
.../RISCV/GISel/RISCVInstructionSelector.cpp | 25 ++++++++++++++
.../GlobalISel/instruction-select/trap.mir | 34 +++++++++++++++++++
2 files changed, 59 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/trap.mir
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 3c72269d1e00c2f..791ce7a855d9888 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -72,6 +72,8 @@ class RISCVInstructionSelector : public InstructionSelector {
MachineRegisterInfo &MRI) const;
bool selectFPCompare(MachineInstr &MI, MachineIRBuilder &MIB,
MachineRegisterInfo &MRI) const;
+ bool selectIntrinsicWithSideEffects(MachineInstr &I, MachineIRBuilder &MIB,
+ MachineRegisterInfo &MRI);
ComplexRendererFns selectShiftMask(MachineOperand &Root) const;
ComplexRendererFns selectAddrRegImm(MachineOperand &Root) const;
@@ -564,6 +566,8 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
return selectSelect(MI, MIB, MRI);
case TargetOpcode::G_FCMP:
return selectFPCompare(MI, MIB, MRI);
+ case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
+ return selectIntrinsicWithSideEffects(MI, MIB, MRI);
default:
return false;
}
@@ -1099,6 +1103,27 @@ bool RISCVInstructionSelector::selectFPCompare(MachineInstr &MI,
return true;
}
+bool RISCVInstructionSelector::selectIntrinsicWithSideEffects(
+ MachineInstr &I, MachineIRBuilder &MIB, MachineRegisterInfo &MRI) {
+ // Find the intrinsic ID.
+ unsigned IntrinID = cast<GIntrinsic>(I).getIntrinsicID();
+
+ // Select the instruction.
+ switch (IntrinID) {
+ default:
+ return false;
+ case Intrinsic::trap:
+ MIB.buildInstr(RISCV::UNIMP, {}, {});
+ break;
+ case Intrinsic::debugtrap:
+ MIB.buildInstr(RISCV::EBREAK, {}, {});
+ break;
+ }
+
+ I.eraseFromParent();
+ return true;
+}
+
namespace llvm {
InstructionSelector *
createRISCVInstructionSelector(const RISCVTargetMachine &TM,
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/trap.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/trap.mir
new file mode 100644
index 000000000000000..11789a030e6fac0
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/trap.mir
@@ -0,0 +1,34 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir \
+# RUN: -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir \
+# RUN: -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: test_trap
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: test_trap
+ ; CHECK: UNIMP
+ ; CHECK-NEXT: PseudoRET
+ G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.trap)
+ PseudoRET
+
+...
+---
+name: test_debugtrap
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: test_debugtrap
+ ; CHECK: EBREAK
+ ; CHECK-NEXT: PseudoRET
+ G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.debugtrap)
+ PseudoRET
+
+...
>From 7eaa822639d825b86827474a2a58c3273e8c024e Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Wed, 22 Nov 2023 13:34:30 -0800
Subject: [PATCH 2/4] fixup! Use MI instead of I for consistency with rest of
file.
---
llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 791ce7a855d9888..e7ac94cddf673a0 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -72,7 +72,7 @@ class RISCVInstructionSelector : public InstructionSelector {
MachineRegisterInfo &MRI) const;
bool selectFPCompare(MachineInstr &MI, MachineIRBuilder &MIB,
MachineRegisterInfo &MRI) const;
- bool selectIntrinsicWithSideEffects(MachineInstr &I, MachineIRBuilder &MIB,
+ bool selectIntrinsicWithSideEffects(MachineInstr &MI, MachineIRBuilder &MIB,
MachineRegisterInfo &MRI);
ComplexRendererFns selectShiftMask(MachineOperand &Root) const;
@@ -1104,9 +1104,9 @@ bool RISCVInstructionSelector::selectFPCompare(MachineInstr &MI,
}
bool RISCVInstructionSelector::selectIntrinsicWithSideEffects(
- MachineInstr &I, MachineIRBuilder &MIB, MachineRegisterInfo &MRI) {
+ MachineInstr &MI, MachineIRBuilder &MIB, MachineRegisterInfo &MRI) {
// Find the intrinsic ID.
- unsigned IntrinID = cast<GIntrinsic>(I).getIntrinsicID();
+ unsigned IntrinID = cast<GIntrinsic>(MI).getIntrinsicID();
// Select the instruction.
switch (IntrinID) {
@@ -1120,7 +1120,7 @@ bool RISCVInstructionSelector::selectIntrinsicWithSideEffects(
break;
}
- I.eraseFromParent();
+ MI.eraseFromParent();
return true;
}
>From 9b17799a5b863b466dfa92df8dcfd84be04ef7d8 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Wed, 22 Nov 2023 21:45:20 -0800
Subject: [PATCH 3/4] fixup! Add const to selectIntrinsicWithSideEffects
---
llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index e7ac94cddf673a0..225cc629638b571 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -73,7 +73,7 @@ class RISCVInstructionSelector : public InstructionSelector {
bool selectFPCompare(MachineInstr &MI, MachineIRBuilder &MIB,
MachineRegisterInfo &MRI) const;
bool selectIntrinsicWithSideEffects(MachineInstr &MI, MachineIRBuilder &MIB,
- MachineRegisterInfo &MRI);
+ MachineRegisterInfo &MRI) const;
ComplexRendererFns selectShiftMask(MachineOperand &Root) const;
ComplexRendererFns selectAddrRegImm(MachineOperand &Root) const;
@@ -1104,7 +1104,7 @@ bool RISCVInstructionSelector::selectFPCompare(MachineInstr &MI,
}
bool RISCVInstructionSelector::selectIntrinsicWithSideEffects(
- MachineInstr &MI, MachineIRBuilder &MIB, MachineRegisterInfo &MRI) {
+ MachineInstr &MI, MachineIRBuilder &MIB, MachineRegisterInfo &MRI) const {
// Find the intrinsic ID.
unsigned IntrinID = cast<GIntrinsic>(MI).getIntrinsicID();
>From ae0f218bb7e614e0d259afda891766422fa8d2d1 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 27 Nov 2023 13:36:45 -0800
Subject: [PATCH 4/4] fixup! Add assert.
---
llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 225cc629638b571..c5dd8676fb7220a 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -1105,6 +1105,8 @@ bool RISCVInstructionSelector::selectFPCompare(MachineInstr &MI,
bool RISCVInstructionSelector::selectIntrinsicWithSideEffects(
MachineInstr &MI, MachineIRBuilder &MIB, MachineRegisterInfo &MRI) const {
+ assert(MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS &&
+ "Unexpected opcode");
// Find the intrinsic ID.
unsigned IntrinID = cast<GIntrinsic>(MI).getIntrinsicID();
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