[llvm] 5f31dbd - [RISCV] Add register bank and instruction selection support for FP G_SELECT. (#72726)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 27 10:38:30 PST 2023
Author: Craig Topper
Date: 2023-11-27T10:38:25-08:00
New Revision: 5f31dbd18d24f0084363891139edf4fe71081eed
URL: https://github.com/llvm/llvm-project/commit/5f31dbd18d24f0084363891139edf4fe71081eed
DIFF: https://github.com/llvm/llvm-project/commit/5f31dbd18d24f0084363891139edf4fe71081eed.diff
LOG: [RISCV] Add register bank and instruction selection support for FP G_SELECT. (#72726)
Try to pick the FP register bank based on surrounding use/defs. Code is
basically copied from AArch64.
Need legalizer changes to make this more useful. Right now we're stuck
with only being able to FP select types less than or equal to XLen.
Added:
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-select-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-select-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv64.mir
Modified:
llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 97fa5106cf7d6c8..3433c3e859b12b5 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -912,8 +912,17 @@ bool RISCVInstructionSelector::selectSelect(MachineInstr &MI,
RISCVCC::CondCode CC;
getOperandsForBranch(SelectMI.getCondReg(), MRI, CC, LHS, RHS);
- MachineInstr *Result = MIB.buildInstr(RISCV::Select_GPR_Using_CC_GPR)
- .addDef(SelectMI.getReg(0))
+ Register DstReg = SelectMI.getReg(0);
+
+ unsigned Opc = RISCV::Select_GPR_Using_CC_GPR;
+ if (RBI.getRegBank(DstReg, MRI, TRI)->getID() == RISCV::FPRBRegBankID) {
+ unsigned Size = MRI.getType(DstReg).getSizeInBits();
+ Opc = Size == 32 ? RISCV::Select_FPR32_Using_CC_GPR
+ : RISCV::Select_FPR64_Using_CC_GPR;
+ }
+
+ MachineInstr *Result = MIB.buildInstr(Opc)
+ .addDef(DstReg)
.addReg(LHS)
.addReg(RHS)
.addImm(CC)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index c2f07e1aa651fe9..a5e453fa5821e5c 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -323,12 +323,57 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
break;
}
- case TargetOpcode::G_SELECT:
- OpdsMapping[0] = GPRValueMapping;
+ case TargetOpcode::G_SELECT: {
+ LLT Ty = MRI.getType(MI.getOperand(0).getReg());
+
+ // Try to minimize the number of copies. If we have more floating point
+ // constrained values than not, then we'll put everything on FPR. Otherwise,
+ // everything has to be on GPR.
+ unsigned NumFP = 0;
+
+ // Check if the uses of the result always produce floating point values.
+ //
+ // For example:
+ //
+ // %z = G_SELECT %cond %x %y
+ // fpr = G_FOO %z ...
+ if (any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),
+ [&](const MachineInstr &UseMI) {
+ return onlyUsesFP(UseMI, MRI, TRI);
+ }))
+ ++NumFP;
+
+ // Check if the defs of the source values always produce floating point
+ // values.
+ //
+ // For example:
+ //
+ // %x = G_SOMETHING_ALWAYS_FLOAT %a ...
+ // %z = G_SELECT %cond %x %y
+ //
+ // Also check whether or not the sources have already been decided to be
+ // FPR. Keep track of this.
+ //
+ // This doesn't check the condition, since the condition is always an
+ // integer.
+ for (unsigned Idx = 2; Idx < 4; ++Idx) {
+ Register VReg = MI.getOperand(Idx).getReg();
+ MachineInstr *DefMI = MRI.getVRegDef(VReg);
+ if (getRegBank(VReg, MRI, TRI) == &RISCV::FPRBRegBank ||
+ onlyDefinesFP(*DefMI, MRI, TRI))
+ ++NumFP;
+ }
+
+ // Condition operand is always GPR.
OpdsMapping[1] = GPRValueMapping;
- OpdsMapping[2] = GPRValueMapping;
- OpdsMapping[3] = GPRValueMapping;
+
+ const ValueMapping *Mapping = GPRValueMapping;
+ if (NumFP >= 2)
+ Mapping = getFPValueMapping(Ty.getSizeInBits());
+
+ OpdsMapping[0] = OpdsMapping[2] = OpdsMapping[3] = Mapping;
break;
+ }
case TargetOpcode::G_FPTOSI:
case TargetOpcode::G_FPTOUI:
case RISCV::G_FCLASS: {
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-select-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-select-rv32.mir
new file mode 100644
index 000000000000000..4fffbc42b2cff34
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-select-rv32.mir
@@ -0,0 +1,33 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=instruction-select \
+# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: fp_select_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $f10_f, $f11_f
+
+ ; CHECK-LABEL: name: fp_select_s32
+ ; CHECK: liveins: $x10, $f10_f, $f11_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f10_f
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $f11_f
+ ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1
+ ; CHECK-NEXT: [[Select_FPR32_Using_CC_GPR:%[0-9]+]]:fpr32 = Select_FPR32_Using_CC_GPR [[ANDI]], $x0, 1, [[COPY1]], [[COPY2]]
+ ; CHECK-NEXT: $f10_f = COPY [[Select_FPR32_Using_CC_GPR]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_f
+ %0:gprb(s32) = COPY $x10
+ %1:fprb(s32) = COPY $f10_f
+ %2:fprb(s32) = COPY $f11_f
+ %3:gprb(s32) = G_CONSTANT i32 1
+ %4:gprb(s32) = G_AND %0, %3
+ %5:fprb(s32) = G_SELECT %4(s32), %1, %2
+ $f10_f = COPY %5(s32)
+ PseudoRET implicit $f10_f
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-select-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-select-rv64.mir
new file mode 100644
index 000000000000000..e291c352e5a8573
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-select-rv64.mir
@@ -0,0 +1,64 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=instruction-select \
+# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: fp_select_s32
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $f10_d, $f11_d
+
+ ; CHECK-LABEL: name: fp_select_s32
+ ; CHECK: liveins: $x10, $f10_d, $f11_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f10_f
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $f11_f
+ ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1
+ ; CHECK-NEXT: [[Select_FPR32_Using_CC_GPR:%[0-9]+]]:fpr32 = Select_FPR32_Using_CC_GPR [[ANDI]], $x0, 1, [[COPY1]], [[COPY2]]
+ ; CHECK-NEXT: $f10_f = COPY [[Select_FPR32_Using_CC_GPR]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_f
+ %0:gprb(s64) = COPY $x10
+ %1:fprb(s32) = COPY $f10_f
+ %2:fprb(s32) = COPY $f11_f
+ %3:gprb(s64) = G_CONSTANT i64 1
+ %4:gprb(s64) = G_AND %0, %3
+ %5:fprb(s32) = G_SELECT %4(s64), %1, %2
+ $f10_f = COPY %5(s32)
+ PseudoRET implicit $f10_f
+
+...
+---
+name: fp_select_s64
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $f10_d, $f11_d
+
+ ; CHECK-LABEL: name: fp_select_s64
+ ; CHECK: liveins: $x10, $f10_d, $f11_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f10_d
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $f11_d
+ ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1
+ ; CHECK-NEXT: [[Select_FPR64_Using_CC_GPR:%[0-9]+]]:fpr64 = Select_FPR64_Using_CC_GPR [[ANDI]], $x0, 1, [[COPY1]], [[COPY2]]
+ ; CHECK-NEXT: $f10_d = COPY [[Select_FPR64_Using_CC_GPR]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_d
+ %0:gprb(s64) = COPY $x10
+ %1:fprb(s64) = COPY $f10_d
+ %2:fprb(s64) = COPY $f11_d
+ %3:gprb(s64) = G_CONSTANT i64 1
+ %4:gprb(s64) = G_AND %0, %3
+ %5:fprb(s64) = G_SELECT %4(s64), %1, %2
+ $f10_d = COPY %5(s64)
+ PseudoRET implicit $f10_d
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv32.mir
new file mode 100644
index 000000000000000..6d8ca3eb6d8271a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv32.mir
@@ -0,0 +1,152 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect \
+# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -o - | FileCheck -check-prefix=RV32I %s
+
+---
+name: fp_select_s32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $f10_f, $f11_f
+
+ ; RV32I-LABEL: name: fp_select_s32
+ ; RV32I: liveins: $x10, $f10_f, $f11_f
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f
+ ; RV32I-NEXT: [[COPY2:%[0-9]+]]:fprb(s32) = COPY $f11_f
+ ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
+ ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]]
+ ; RV32I-NEXT: [[SELECT:%[0-9]+]]:fprb(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
+ ; RV32I-NEXT: $f10_f = COPY [[SELECT]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $f10_f
+ %3:_(s32) = COPY $x10
+ %4:_(s32) = COPY $f10_f
+ %5:_(s32) = COPY $f11_f
+ %12:_(s32) = G_CONSTANT i32 1
+ %11:_(s32) = G_AND %3, %12
+ %10:_(s32) = G_SELECT %11(s32), %4, %5
+ $f10_f = COPY %10(s32)
+ PseudoRET implicit $f10_f
+
+...
+---
+name: fp_select_gpr_use_s32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $f10_f, $f11_f
+
+ ; RV32I-LABEL: name: fp_select_gpr_use_s32
+ ; RV32I: liveins: $x10, $f10_f, $f11_f
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f
+ ; RV32I-NEXT: [[COPY2:%[0-9]+]]:fprb(s32) = COPY $f11_f
+ ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
+ ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]]
+ ; RV32I-NEXT: [[SELECT:%[0-9]+]]:fprb(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
+ ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ %3:_(s32) = COPY $x10
+ %4:_(s32) = COPY $f10_f
+ %5:_(s32) = COPY $f11_f
+ %12:_(s32) = G_CONSTANT i32 1
+ %11:_(s32) = G_AND %3, %12
+ %10:_(s32) = G_SELECT %11(s32), %4, %5
+ $x10 = COPY %10(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fp_select_gpr_def_s32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11, $f10_f
+
+ ; RV32I-LABEL: name: fp_select_gpr_def_s32
+ ; RV32I: liveins: $x10, $x11, $f10_f
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f
+ ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $x11
+ ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
+ ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]]
+ ; RV32I-NEXT: [[COPY3:%[0-9]+]]:fprb(s32) = COPY [[COPY2]](s32)
+ ; RV32I-NEXT: [[SELECT:%[0-9]+]]:fprb(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY3]]
+ ; RV32I-NEXT: $f10_f = COPY [[SELECT]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $f10_f
+ %3:_(s32) = COPY $x10
+ %4:_(s32) = COPY $f10_f
+ %5:_(s32) = COPY $x11
+ %12:_(s32) = G_CONSTANT i32 1
+ %11:_(s32) = G_AND %3, %12
+ %10:_(s32) = G_SELECT %11(s32), %4, %5
+ $f10_f = COPY %10(s32)
+ PseudoRET implicit $f10_f
+
+...
+---
+name: fp_select_only_fpr_use_s32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11, $x12
+
+ ; RV32I-LABEL: name: fp_select_only_fpr_use_s32
+ ; RV32I: liveins: $x10, $x11, $x12
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+ ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $x12
+ ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
+ ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]]
+ ; RV32I-NEXT: [[SELECT:%[0-9]+]]:gprb(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
+ ; RV32I-NEXT: $f10_f = COPY [[SELECT]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $f10_f
+ %3:_(s32) = COPY $x10
+ %4:_(s32) = COPY $x11
+ %5:_(s32) = COPY $x12
+ %12:_(s32) = G_CONSTANT i32 1
+ %11:_(s32) = G_AND %3, %12
+ %10:_(s32) = G_SELECT %11(s32), %4, %5
+ $f10_f = COPY %10(s32)
+ PseudoRET implicit $f10_f
+
+...
+---
+name: fp_select_only_one_fpr_def_s32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11, $f10_f
+
+ ; RV32I-LABEL: name: fp_select_only_one_fpr_def_s32
+ ; RV32I: liveins: $x10, $x11, $f10_f
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f
+ ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $x11
+ ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
+ ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]]
+ ; RV32I-NEXT: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[COPY1]](s32)
+ ; RV32I-NEXT: [[SELECT:%[0-9]+]]:gprb(s32) = G_SELECT [[AND]](s32), [[COPY3]], [[COPY2]]
+ ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ %3:_(s32) = COPY $x10
+ %4:_(s32) = COPY $f10_f
+ %5:_(s32) = COPY $x11
+ %12:_(s32) = G_CONSTANT i32 1
+ %11:_(s32) = G_AND %3, %12
+ %10:_(s32) = G_SELECT %11(s32), %4, %5
+ $x10 = COPY %10(s32)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv64.mir
new file mode 100644
index 000000000000000..1ecee1643daac9d
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv64.mir
@@ -0,0 +1,245 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect \
+# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -o - | FileCheck -check-prefix=RV32I %s
+
+---
+name: fp_select_s32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $f10_f, $f11_f
+
+ ; RV32I-LABEL: name: fp_select_s32
+ ; RV32I: liveins: $x10, $f10_f, $f11_f
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f
+ ; RV32I-NEXT: [[COPY2:%[0-9]+]]:fprb(s32) = COPY $f11_f
+ ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1
+ ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s64) = G_AND [[COPY]], [[C]]
+ ; RV32I-NEXT: [[SELECT:%[0-9]+]]:fprb(s32) = G_SELECT [[AND]](s64), [[COPY1]], [[COPY2]]
+ ; RV32I-NEXT: $f10_f = COPY [[SELECT]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $f10_f
+ %3:_(s64) = COPY $x10
+ %4:_(s32) = COPY $f10_f
+ %5:_(s32) = COPY $f11_f
+ %12:_(s64) = G_CONSTANT i64 1
+ %11:_(s64) = G_AND %3, %12
+ %10:_(s32) = G_SELECT %11(s64), %4(s32), %5
+ $f10_f = COPY %10(s32)
+ PseudoRET implicit $f10_f
+
+...
+---
+name: fp_select_s64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $f10_d, $f11_d
+
+ ; RV32I-LABEL: name: fp_select_s64
+ ; RV32I: liveins: $x10, $f10_d, $f11_d
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
+ ; RV32I-NEXT: [[COPY2:%[0-9]+]]:fprb(s64) = COPY $f11_d
+ ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1
+ ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s64) = G_AND [[COPY]], [[C]]
+ ; RV32I-NEXT: [[SELECT:%[0-9]+]]:fprb(s64) = G_SELECT [[AND]](s64), [[COPY1]], [[COPY2]]
+ ; RV32I-NEXT: $f10_d = COPY [[SELECT]](s64)
+ ; RV32I-NEXT: PseudoRET implicit $f10_d
+ %3:_(s64) = COPY $x10
+ %4:_(s64) = COPY $f10_d
+ %5:_(s64) = COPY $f11_d
+ %12:_(s64) = G_CONSTANT i64 1
+ %11:_(s64) = G_AND %3, %12
+ %10:_(s64) = G_SELECT %11(s64), %4, %5
+ $f10_d = COPY %10(s64)
+ PseudoRET implicit $f10_d
+
+...
+---
+name: fp_select_gpr_use_s32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $f10_f, $f11_f
+
+ ; RV32I-LABEL: name: fp_select_gpr_use_s32
+ ; RV32I: liveins: $x10, $f10_f, $f11_f
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f
+ ; RV32I-NEXT: [[COPY2:%[0-9]+]]:fprb(s32) = COPY $f11_f
+ ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1
+ ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s64) = G_AND [[COPY]], [[C]]
+ ; RV32I-NEXT: [[SELECT:%[0-9]+]]:fprb(s32) = G_SELECT [[AND]](s64), [[COPY1]], [[COPY2]]
+ ; RV32I-NEXT: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[SELECT]](s32)
+ ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[COPY3]](s32)
+ ; RV32I-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ %3:_(s64) = COPY $x10
+ %4:_(s32) = COPY $f10_f
+ %5:_(s32) = COPY $f11_f
+ %12:_(s64) = G_CONSTANT i64 1
+ %11:_(s64) = G_AND %3, %12
+ %10:_(s32) = G_SELECT %11(s64), %4(s32), %5
+ %13:_(s64) = G_ANYEXT %10(s32)
+ $x10 = COPY %13(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fp_select_gpr_use_s64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $f10_d, $f11_d
+
+ ; RV32I-LABEL: name: fp_select_gpr_use_s64
+ ; RV32I: liveins: $x10, $f10_d, $f11_d
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
+ ; RV32I-NEXT: [[COPY2:%[0-9]+]]:fprb(s64) = COPY $f11_d
+ ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1
+ ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s64) = G_AND [[COPY]], [[C]]
+ ; RV32I-NEXT: [[SELECT:%[0-9]+]]:fprb(s64) = G_SELECT [[AND]](s64), [[COPY1]], [[COPY2]]
+ ; RV32I-NEXT: $x10 = COPY [[SELECT]](s64)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ %3:_(s64) = COPY $x10
+ %4:_(s64) = COPY $f10_d
+ %5:_(s64) = COPY $f11_d
+ %12:_(s64) = G_CONSTANT i64 1
+ %11:_(s64) = G_AND %3, %12
+ %10:_(s64) = G_SELECT %11(s64), %4, %5
+ $x10 = COPY %10(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fp_select_gpr_def_s32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11, $f10_f
+
+ ; RV32I-LABEL: name: fp_select_gpr_def_s32
+ ; RV32I: liveins: $x10, $x11, $f10_f
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f
+ ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gprb(s64) = COPY $x11
+ ; RV32I-NEXT: [[TRUNC:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY2]](s64)
+ ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1
+ ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s64) = G_AND [[COPY]], [[C]]
+ ; RV32I-NEXT: [[COPY3:%[0-9]+]]:fprb(s32) = COPY [[TRUNC]](s32)
+ ; RV32I-NEXT: [[SELECT:%[0-9]+]]:fprb(s32) = G_SELECT [[AND]](s64), [[COPY3]], [[COPY1]]
+ ; RV32I-NEXT: $f10_f = COPY [[SELECT]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $f10_f
+ %3:_(s64) = COPY $x10
+ %4:_(s32) = COPY $f10_f
+ %5:_(s64) = COPY $x11
+ %6:_(s32) = G_TRUNC %5(s64)
+ %12:_(s64) = G_CONSTANT i64 1
+ %11:_(s64) = G_AND %3, %12
+ %10:_(s32) = G_SELECT %11(s64), %6(s32), %4
+ $f10_f = COPY %10(s32)
+ PseudoRET implicit $f10_f
+
+...
+---
+name: fp_select_gpr_def_s64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11, $f10_d
+
+ ; RV32I-LABEL: name: fp_select_gpr_def_s64
+ ; RV32I: liveins: $x10, $x11, $f10_d
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
+ ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gprb(s64) = COPY $x11
+ ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1
+ ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s64) = G_AND [[COPY]], [[C]]
+ ; RV32I-NEXT: [[COPY3:%[0-9]+]]:fprb(s64) = COPY [[COPY2]](s64)
+ ; RV32I-NEXT: [[SELECT:%[0-9]+]]:fprb(s64) = G_SELECT [[AND]](s64), [[COPY1]], [[COPY3]]
+ ; RV32I-NEXT: $f10_d = COPY [[SELECT]](s64)
+ ; RV32I-NEXT: PseudoRET implicit $f10_d
+ %3:_(s64) = COPY $x10
+ %4:_(s64) = COPY $f10_d
+ %5:_(s64) = COPY $x11
+ %12:_(s64) = G_CONSTANT i64 1
+ %11:_(s64) = G_AND %3, %12
+ %10:_(s64) = G_SELECT %11(s64), %4, %5
+ $f10_d = COPY %10(s64)
+ PseudoRET implicit $f10_d
+
+...
+---
+name: fp_select_only_fpr_use_s64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11, $x12
+
+ ; RV32I-LABEL: name: fp_select_only_fpr_use_s64
+ ; RV32I: liveins: $x10, $x11, $x12
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+ ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gprb(s64) = COPY $x12
+ ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1
+ ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s64) = G_AND [[COPY]], [[C]]
+ ; RV32I-NEXT: [[SELECT:%[0-9]+]]:gprb(s64) = G_SELECT [[AND]](s64), [[COPY1]], [[COPY2]]
+ ; RV32I-NEXT: $f10_d = COPY [[SELECT]](s64)
+ ; RV32I-NEXT: PseudoRET implicit $f10_d
+ %3:_(s64) = COPY $x10
+ %4:_(s64) = COPY $x11
+ %5:_(s64) = COPY $x12
+ %12:_(s64) = G_CONSTANT i64 1
+ %11:_(s64) = G_AND %3, %12
+ %10:_(s64) = G_SELECT %11(s64), %4, %5
+ $f10_d = COPY %10(s64)
+ PseudoRET implicit $f10_d
+
+...
+---
+name: fp_select_only_one_fpr_def_s64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11, $f10_d
+
+ ; RV32I-LABEL: name: fp_select_only_one_fpr_def_s64
+ ; RV32I: liveins: $x10, $x11, $f10_d
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
+ ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gprb(s64) = COPY $x11
+ ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1
+ ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s64) = G_AND [[COPY]], [[C]]
+ ; RV32I-NEXT: [[COPY3:%[0-9]+]]:gprb(s64) = COPY [[COPY1]](s64)
+ ; RV32I-NEXT: [[SELECT:%[0-9]+]]:gprb(s64) = G_SELECT [[AND]](s64), [[COPY3]], [[COPY2]]
+ ; RV32I-NEXT: $x10 = COPY [[SELECT]](s64)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ %3:_(s64) = COPY $x10
+ %4:_(s64) = COPY $f10_d
+ %5:_(s64) = COPY $x11
+ %12:_(s64) = G_CONSTANT i64 1
+ %11:_(s64) = G_AND %3, %12
+ %10:_(s64) = G_SELECT %11(s64), %4, %5
+ $x10 = COPY %10(s64)
+ PseudoRET implicit $x10
+
+...
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