[llvm] 811234e - [RISCV] Add Zbs Write classes to SiFive7AnyToGPRBypass. (#72560)

[via llvm-commits]

Author: Craig Topper
Date: 2023-11-27T09:06:37-08:00
New Revision: 811234ee954a2d7e3c4e91aab390e87f4a36e9b9

URL: https://github.com/llvm/llvm-project/commit/811234ee954a2d7e3c4e91aab390e87f4a36e9b9
DIFF: https://github.com/llvm/llvm-project/commit/811234ee954a2d7e3c4e91aab390e87f4a36e9b9.diff

LOG: [RISCV] Add Zbs Write classes to SiFive7AnyToGPRBypass. (#72560)

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index 9da68dc9a139d32..53ef9d1baf7b59a 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -182,6 +182,8 @@ class SiFive7AnyToGPRBypass<SchedRead read, int cycles = 2>
                                  WriteSHXADD, WriteSHXADD32,
                                  WriteRotateImm, WriteRotateImm32,
                                  WriteRotateReg, WriteRotateReg32,
+                                 WriteSingleBit, WriteSingleBitImm,
+                                 WriteBEXT, WriteBEXTI,
                                  WriteCLZ, WriteCLZ32, WriteCTZ, WriteCTZ32,
                                  WriteCPOP, WriteCPOP32,
                                  WriteREV8, WriteORCB, WriteSFB,