[llvm] [RISCV] Add register bank and instruction selection support for FP G_SELECT. (PR #72726)

[Michael Maitland via llvm-commits]

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@@ -323,12 +323,57 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
       OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
     break;
   }
-  case TargetOpcode::G_SELECT:
-    OpdsMapping[0] = GPRValueMapping;
+  case TargetOpcode::G_SELECT: {
+    LLT Ty = MRI.getType(MI.getOperand(0).getReg());
+
+    // Try to minimize the number of copies. If we have more floating point
+    // constrained values than not, then we'll put everything on FPR. Otherwise,
+    // everything has to be on GPR.
+    unsigned NumFP = 0;
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michaelmaitland wrote:

It looks like there are two ways for NumFP to get an increment:
1. The def of G_SELECT is used by an instruction that onlyUsesFP operands.
2. The true and false operands of G_SELECT are FPRB already or were defined by an instruction that onlyDefinesFP.

It is unclear what is meant by "If we have more floating point constrained values than not". It sounds like the set of values being considered is the true value, the false value, and the values defined by instructions that use the def of the G_SELECT. However, below we use FP when `NumFP >= 2`. I think the statement made in this comment does not say the same thing as this condition. For example, if there are 10 uses of the result of this G_SELECT, it is possible that we have more GPR than FPR, but `NumFP >= 2` can still be true.

https://github.com/llvm/llvm-project/pull/72726