[llvm] [AArch64] Update comment on GHC CC (PR #72761)

[Aiden Grossman via llvm-commits]

https://github.com/boomanaiden154 updated https://github.com/llvm/llvm-project/pull/72761

>From 92bd193f3c993673b5d7b40a448a0b19b856efeb Mon Sep 17 00:00:00 2001
From: Aiden Grossman <agrossman154 at yahoo.com>
Date: Sat, 18 Nov 2023 13:13:41 -0800
Subject: [PATCH 1/2] [AArch64] Update comment on GHC CC

Currently, there are a couple dead links in the comment surrounding the
tablegen implementtion of the GHC calling convention in AArch64. There
was some refactoring in GHC that moved things around. This patch fixes
up the comment to match the current state of the repository to make it
easier for future readers to reference the relevant documentation.
---
 llvm/lib/Target/AArch64/AArch64CallingConvention.td | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64CallingConvention.td b/llvm/lib/Target/AArch64/AArch64CallingConvention.td
index 4993b995d881f25..9878d8c0034d61f 100644
--- a/llvm/lib/Target/AArch64/AArch64CallingConvention.td
+++ b/llvm/lib/Target/AArch64/AArch64CallingConvention.td
@@ -333,7 +333,7 @@ def CC_AArch64_DarwinPCS_ILP32_VarArg : CallingConv<[
 // The only documentation is the GHC source code, specifically the C header
 // file:
 //
-//     https://github.com/ghc/ghc/blob/master/includes/stg/MachRegs.h
+//    https://github.com/ghc/ghc/blob/master/rts/include/stg/MachRegs.h
 //
 // which defines the registers for the Spineless Tagless G-Machine (STG) that
 // GHC uses to implement lazy evaluation. The generic STG machine has a set of
@@ -344,8 +344,10 @@ def CC_AArch64_DarwinPCS_ILP32_VarArg : CallingConv<[
 //
 //    https://ghc.haskell.org/trac/ghc/wiki/Commentary/Compiler/GeneratedCode
 //
-// The AArch64 register mapping is under the heading "The ARMv8/AArch64 ABI
-// register mapping".
+// The AArch64 register mapping is defined in the following header file:
+//
+//    https://github.com/ghc/ghc/blob/master/rts/include/stg/MachRegs/arm32.h
+//
 
 let Entry = 1 in
 def CC_AArch64_GHC : CallingConv<[

>From 8572b6e5cbef87d0a01214cec435a17b73bedcd8 Mon Sep 17 00:00:00 2001
From: Aiden Grossman <agrossman154 at yahoo.com>
Date: Mon, 27 Nov 2023 00:33:15 -0800
Subject: [PATCH 2/2] Switch link to register mappings

---
 llvm/lib/Target/AArch64/AArch64CallingConvention.td | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AArch64/AArch64CallingConvention.td b/llvm/lib/Target/AArch64/AArch64CallingConvention.td
index 9878d8c0034d61f..e47996bf38d457b 100644
--- a/llvm/lib/Target/AArch64/AArch64CallingConvention.td
+++ b/llvm/lib/Target/AArch64/AArch64CallingConvention.td
@@ -346,7 +346,7 @@ def CC_AArch64_DarwinPCS_ILP32_VarArg : CallingConv<[
 //
 // The AArch64 register mapping is defined in the following header file:
 //
-//    https://github.com/ghc/ghc/blob/master/rts/include/stg/MachRegs/arm32.h
+//    https://github.com/ghc/ghc/blob/master/rts/include/stg/MachRegs/arm64.h
 //
 
 let Entry = 1 in