[llvm] [AArch64][GlobalISel] Add legalization for vecreduce.fmul (PR #73309)

[Amara Emerson via llvm-commits]

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@@ -977,6 +977,19 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
       .clampMaxNumElements(1, s32, 2)
       .lower();
 
+  // For fmul reductions we need to split up into individual operations. We
+  // clamp to 128 bit vectors then to 64bit vectors to produce a cascade of
+  // smaller types, followed by scalarizing what remains.
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aemerson wrote:

If you add a MIR test it's easier to see what it's doing.

https://github.com/llvm/llvm-project/pull/73309