[llvm] [AMDGPU][True16] Support V_CEIL_F16. (PR #73108)

Ivan Kosarev via llvm-commits llvm-commits at lists.llvm.org
Fri Nov 24 03:17:12 PST 2023


https://github.com/kosarev updated https://github.com/llvm/llvm-project/pull/73108

>From 188502ef0ec11a6f3e61c13e95bb45212b867dd8 Mon Sep 17 00:00:00 2001
From: Ivan Kosarev <ivan.kosarev at amd.com>
Date: Tue, 21 Nov 2023 17:04:05 +0000
Subject: [PATCH 1/2] [AMDGPU][True16] Pre-commit V_CEIL_F16 tests.

---
 .../GlobalISel/inst-select-fceil.s16.mir      | 82 ++++++++++++++-----
 .../CodeGen/AMDGPU/fix-sgpr-copies-f16.mir    | 18 +++-
 llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll     | 47 ++++++++++-
 llvm/test/MC/AMDGPU/gfx11_asm_vop1-fake16.s   | 47 +++++++++++
 .../MC/AMDGPU/gfx11_asm_vop1_dpp16-fake16.s   | 44 ++++++++++
 .../MC/AMDGPU/gfx11_asm_vop1_dpp8-fake16.s    | 11 +++
 .../MC/AMDGPU/gfx11_asm_vop1_t16_err-fake16.s | 23 ++++++
 .../MC/AMDGPU/gfx11_unsupported_sdwa-fake16.s |  5 ++
 8 files changed, 256 insertions(+), 21 deletions(-)
 create mode 100644 llvm/test/MC/AMDGPU/gfx11_asm_vop1-fake16.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16-fake16.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp8-fake16.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err-fake16.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx11_unsupported_sdwa-fake16.s

diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir
index d9ba03f95a1cfba..70ed03376ae49b9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir
@@ -1,5 +1,7 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefixes=GCN,GFX8 %s
+# RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefixes=GCN,GFX11 %s
+# RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefixes=GCN,GFX11-FAKE16 %s
 
 ---
 name: fceil_s16_ss
@@ -36,12 +38,26 @@ body: |
   bb.0:
     liveins: $vgpr0
 
-    ; GCN-LABEL: name: fceil_s16_vv
-    ; GCN: liveins: $vgpr0
-    ; GCN-NEXT: {{  $}}
-    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; GCN-NEXT: %2:vgpr_32 = nofpexcept V_CEIL_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
-    ; GCN-NEXT: $vgpr0 = COPY %2
+    ; GFX8-LABEL: name: fceil_s16_vv
+    ; GFX8: liveins: $vgpr0
+    ; GFX8-NEXT: {{  $}}
+    ; GFX8-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GFX8-NEXT: [[V_CEIL_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CEIL_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
+    ; GFX8-NEXT: $vgpr0 = COPY [[V_CEIL_F16_e64_]]
+    ;
+    ; GFX11-LABEL: name: fceil_s16_vv
+    ; GFX11: liveins: $vgpr0
+    ; GFX11-NEXT: {{  $}}
+    ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GFX11-NEXT: [[V_CEIL_F16_t16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CEIL_F16_t16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
+    ; GFX11-NEXT: $vgpr0 = COPY [[V_CEIL_F16_t16_e64_]]
+    ;
+    ; GFX11-FAKE16-LABEL: name: fceil_s16_vv
+    ; GFX11-FAKE16: liveins: $vgpr0
+    ; GFX11-FAKE16-NEXT: {{  $}}
+    ; GFX11-FAKE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GFX11-FAKE16-NEXT: [[V_CEIL_F16_t16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CEIL_F16_t16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
+    ; GFX11-FAKE16-NEXT: $vgpr0 = COPY [[V_CEIL_F16_t16_e64_]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s16) = G_TRUNC %0
     %2:vgpr(s16) = G_FCEIL %1
@@ -59,12 +75,26 @@ body: |
   bb.0:
     liveins: $sgpr0
 
-    ; GCN-LABEL: name: fceil_s16_vs
-    ; GCN: liveins: $sgpr0
-    ; GCN-NEXT: {{  $}}
-    ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; GCN-NEXT: %2:vgpr_32 = nofpexcept V_CEIL_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
-    ; GCN-NEXT: $vgpr0 = COPY %2
+    ; GFX8-LABEL: name: fceil_s16_vs
+    ; GFX8: liveins: $sgpr0
+    ; GFX8-NEXT: {{  $}}
+    ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; GFX8-NEXT: [[V_CEIL_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CEIL_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
+    ; GFX8-NEXT: $vgpr0 = COPY [[V_CEIL_F16_e64_]]
+    ;
+    ; GFX11-LABEL: name: fceil_s16_vs
+    ; GFX11: liveins: $sgpr0
+    ; GFX11-NEXT: {{  $}}
+    ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; GFX11-NEXT: [[V_CEIL_F16_t16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CEIL_F16_t16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
+    ; GFX11-NEXT: $vgpr0 = COPY [[V_CEIL_F16_t16_e64_]]
+    ;
+    ; GFX11-FAKE16-LABEL: name: fceil_s16_vs
+    ; GFX11-FAKE16: liveins: $sgpr0
+    ; GFX11-FAKE16-NEXT: {{  $}}
+    ; GFX11-FAKE16-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; GFX11-FAKE16-NEXT: [[V_CEIL_F16_t16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CEIL_F16_t16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
+    ; GFX11-FAKE16-NEXT: $vgpr0 = COPY [[V_CEIL_F16_t16_e64_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s16) = G_TRUNC %0
     %2:vgpr(s16) = G_FCEIL %1
@@ -82,12 +112,26 @@ body: |
   bb.0:
     liveins: $vgpr0
 
-    ; GCN-LABEL: name: fceil_fneg_s16_vv
-    ; GCN: liveins: $vgpr0
-    ; GCN-NEXT: {{  $}}
-    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; GCN-NEXT: %3:vgpr_32 = nofpexcept V_CEIL_F16_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec
-    ; GCN-NEXT: $vgpr0 = COPY %3
+    ; GFX8-LABEL: name: fceil_fneg_s16_vv
+    ; GFX8: liveins: $vgpr0
+    ; GFX8-NEXT: {{  $}}
+    ; GFX8-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GFX8-NEXT: [[V_CEIL_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CEIL_F16_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec
+    ; GFX8-NEXT: $vgpr0 = COPY [[V_CEIL_F16_e64_]]
+    ;
+    ; GFX11-LABEL: name: fceil_fneg_s16_vv
+    ; GFX11: liveins: $vgpr0
+    ; GFX11-NEXT: {{  $}}
+    ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GFX11-NEXT: [[V_CEIL_F16_t16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CEIL_F16_t16_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec
+    ; GFX11-NEXT: $vgpr0 = COPY [[V_CEIL_F16_t16_e64_]]
+    ;
+    ; GFX11-FAKE16-LABEL: name: fceil_fneg_s16_vv
+    ; GFX11-FAKE16: liveins: $vgpr0
+    ; GFX11-FAKE16-NEXT: {{  $}}
+    ; GFX11-FAKE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GFX11-FAKE16-NEXT: [[V_CEIL_F16_t16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CEIL_F16_t16_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec
+    ; GFX11-FAKE16-NEXT: $vgpr0 = COPY [[V_CEIL_F16_t16_e64_]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s16) = G_TRUNC %0
     %2:vgpr(s16) = G_FNEG %1
diff --git a/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16.mir b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16.mir
index 5eafe8b261f4462..a8f7a66d9b71aa2 100644
--- a/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16.mir
+++ b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
-# RUN: llc -march=amdgcn -mcpu=gfx1100 -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
+# RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN %s
+# RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN %s
 
 ---
 name:            cmp_f16
@@ -56,3 +57,18 @@ body:             |
     %4:sreg_32 = COPY %3:vgpr_32
     %5:sreg_32 = nofpexcept S_FMAC_F16 killed %1:sreg_32, %2:sreg_32, %4:sreg_32, implicit $mode
 ...
+
+---
+name:            ceil_f16
+body:             |
+  bb.0:
+    ; GCN-LABEL: name: ceil_f16
+    ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+    ; GCN-NEXT: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[DEF]], 0, 0, implicit $mode, implicit $exec
+    ; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+    ; GCN-NEXT: [[V_CEIL_F16_t16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CEIL_F16_t16_e64 0, [[V_CVT_F32_U32_e64_]], 0, 0, implicit $mode, implicit $exec
+    %0:vgpr_32 = IMPLICIT_DEF
+    %1:vgpr_32 = V_CVT_F32_U32_e64 %0:vgpr_32, 0, 0, implicit $mode, implicit $exec
+    %2:sreg_32 = COPY %1:vgpr_32
+    %3:sreg_32 = nofpexcept S_CEIL_F16 killed %2:sreg_32, implicit $mode
+...
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
index 0c4d952995aebe1..41b9426eba26732 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
@@ -1,7 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=SI %s
 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=VI %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx1100 -mattr=+real-true16,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx1100 -mattr=-real-true16,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11-FAKE16 %s
 
 declare half @llvm.ceil.f16(half %a)
 declare <2 x half> @llvm.ceil.v2f16(<2 x half> %a)
@@ -64,6 +65,26 @@ define amdgpu_kernel void @ceil_f16(
 ; GFX11-NEXT:    s_nop 0
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: ceil_f16:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[0:1], 0x24
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, -1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX11-FAKE16-NEXT:    s_mov_b32 s10, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s11, s7
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s8, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s9, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s0
+; GFX11-FAKE16-NEXT:    buffer_load_u16 v0, off, s[8:11], 0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_ceil_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    buffer_store_b16 v0, off, s[4:7], 0
+; GFX11-FAKE16-NEXT:    s_nop 0
+; GFX11-FAKE16-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a) {
 entry:
@@ -150,6 +171,30 @@ define amdgpu_kernel void @ceil_v2f16(
 ; GFX11-NEXT:    s_nop 0
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: ceil_v2f16:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[0:1], 0x24
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, -1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX11-FAKE16-NEXT:    s_mov_b32 s10, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s11, s7
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s8, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s9, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s0
+; GFX11-FAKE16-NEXT:    buffer_load_b32 v0, off, s[8:11], 0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-FAKE16-NEXT:    v_ceil_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_ceil_f16_e32 v1, v1
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-FAKE16-NEXT:    buffer_store_b32 v0, off, s[4:7], 0
+; GFX11-FAKE16-NEXT:    s_nop 0
+; GFX11-FAKE16-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a) {
 entry:
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop1-fake16.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop1-fake16.s
new file mode 100644
index 000000000000000..668085cffbf0043
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop1-fake16.s
@@ -0,0 +1,47 @@
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-real-true16,+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-real-true16,-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
+
+v_ceil_f16 v5, v1
+// GFX11: encoding: [0x01,0xb9,0x0a,0x7e]
+
+v_ceil_f16 v5, v127
+// GFX11: encoding: [0x7f,0xb9,0x0a,0x7e]
+
+v_ceil_f16 v5, s1
+// GFX11: encoding: [0x01,0xb8,0x0a,0x7e]
+
+v_ceil_f16 v5, s105
+// GFX11: encoding: [0x69,0xb8,0x0a,0x7e]
+
+v_ceil_f16 v5, vcc_lo
+// GFX11: encoding: [0x6a,0xb8,0x0a,0x7e]
+
+v_ceil_f16 v5, vcc_hi
+// GFX11: encoding: [0x6b,0xb8,0x0a,0x7e]
+
+v_ceil_f16 v5, ttmp15
+// GFX11: encoding: [0x7b,0xb8,0x0a,0x7e]
+
+v_ceil_f16 v5, m0
+// GFX11: encoding: [0x7d,0xb8,0x0a,0x7e]
+
+v_ceil_f16 v5, exec_lo
+// GFX11: encoding: [0x7e,0xb8,0x0a,0x7e]
+
+v_ceil_f16 v5, exec_hi
+// GFX11: encoding: [0x7f,0xb8,0x0a,0x7e]
+
+v_ceil_f16 v5, null
+// GFX11: encoding: [0x7c,0xb8,0x0a,0x7e]
+
+v_ceil_f16 v5, -1
+// GFX11: encoding: [0xc1,0xb8,0x0a,0x7e]
+
+v_ceil_f16 v5, 0.5
+// GFX11: encoding: [0xf0,0xb8,0x0a,0x7e]
+
+v_ceil_f16 v5, src_scc
+// GFX11: encoding: [0xfd,0xb8,0x0a,0x7e]
+
+v_ceil_f16 v127, 0xfe0b
+// GFX11: encoding: [0xff,0xb8,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16-fake16.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16-fake16.s
new file mode 100644
index 000000000000000..e3679b9321f439b
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16-fake16.s
@@ -0,0 +1,44 @@
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-real-true16,+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-real-true16,-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+
+v_ceil_f16 v5, v1 quad_perm:[3,2,1,0]
+// GFX11: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_ceil_f16 v5, v1 quad_perm:[0,1,2,3]
+// GFX11: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_ceil_f16 v5, v1 row_mirror
+// GFX11: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_ceil_f16 v5, v1 row_half_mirror
+// GFX11: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_ceil_f16 v5, v1 row_shl:1
+// GFX11: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_ceil_f16 v5, v1 row_shl:15
+// GFX11: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_ceil_f16 v5, v1 row_shr:1
+// GFX11: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_ceil_f16 v5, v1 row_shr:15
+// GFX11: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_ceil_f16 v5, v1 row_ror:1
+// GFX11: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_ceil_f16 v5, v1 row_ror:15
+// GFX11: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_ceil_f16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX11: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_ceil_f16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX11: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_ceil_f16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX11: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_ceil_f16 v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX11: encoding: [0xfa,0xb8,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp8-fake16.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp8-fake16.s
new file mode 100644
index 000000000000000..b6573c9778d80d6
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp8-fake16.s
@@ -0,0 +1,11 @@
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-real-true16,+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-real-true16,-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+
+v_ceil_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0xe9,0xb8,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_ceil_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX11: encoding: [0xea,0xb8,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_ceil_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX11: encoding: [0xe9,0xb8,0xfe,0x7e,0x7f,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err-fake16.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err-fake16.s
new file mode 100644
index 000000000000000..d6f317ee0829bb9
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err-fake16.s
@@ -0,0 +1,23 @@
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-real-true16,+wavefrontsize32,-wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-real-true16,-wavefrontsize32,+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
+
+v_ceil_f16_e32 v128, 0xfe0b
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_ceil_f16_e32 v255, v1
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_ceil_f16_e32 v5, v199
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_ceil_f16_e32 v255, v1 quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_ceil_f16_e32 v5, v199 quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_ceil_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_ceil_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
diff --git a/llvm/test/MC/AMDGPU/gfx11_unsupported_sdwa-fake16.s b/llvm/test/MC/AMDGPU/gfx11_unsupported_sdwa-fake16.s
new file mode 100644
index 000000000000000..737256d6b727a2d
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx11_unsupported_sdwa-fake16.s
@@ -0,0 +1,5 @@
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-real-true16,+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-real-true16,-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+
+v_ceil_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported

>From 8791ab6b931e357aebde64a92f2015463d20f3f0 Mon Sep 17 00:00:00 2001
From: Ivan Kosarev <ivan.kosarev at amd.com>
Date: Tue, 21 Nov 2023 13:44:22 +0000
Subject: [PATCH 2/2] [AMDGPU][True16] Support V_CEIL_F16.

As not all fake instructions have their real counterparts implemented
yet, we specify no AssemblerPredicate for UseFakeTrue16Insts to allow
both fake and real True16 instructions in assembler and disassembler
tests in the -mattr=+real-true16 mode during the transition period.

Source DPP and desitnation VOPDstOperand_t16 operands are still not
supported and will be addressed separately.
---
 .../AMDGPU/AsmParser/AMDGPUAsmParser.cpp      | 55 +++++++++++-----
 llvm/lib/Target/AMDGPU/SIInstrInfo.cpp        | 23 +++++--
 llvm/lib/Target/AMDGPU/VOP1Instructions.td    | 62 +++++++++++-------
 .../GlobalISel/inst-select-fceil.s16.mir      | 35 ++++++----
 .../CodeGen/AMDGPU/fix-sgpr-copies-f16.mir    | 20 ++++--
 llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll     | 11 ++--
 llvm/test/MC/AMDGPU/gfx11_asm_vop1.s          | 46 +++++++------
 llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16.s    | 38 +++++------
 llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp8.s     | 17 +++--
 llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s  | 46 +++++++++----
 llvm/test/MC/AMDGPU/gfx11_unsupported_sdwa.s  |  6 +-
 .../Disassembler/AMDGPU/gfx11_dasm_vop1.txt   | 65 +++++++++++++------
 12 files changed, 270 insertions(+), 154 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index be74c627d213756..5f20cc7310fdc05 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -50,6 +50,8 @@ class AMDGPUAsmParser;
 
 enum RegisterKind { IS_UNKNOWN, IS_VGPR, IS_SGPR, IS_AGPR, IS_TTMP, IS_SPECIAL };
 
+enum class RegisterSuffix { None, Lo, Hi };
+
 //===----------------------------------------------------------------------===//
 // Operand
 //===----------------------------------------------------------------------===//
@@ -1333,10 +1335,8 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
   unsigned ParseRegList(RegisterKind &RegKind, unsigned &RegNum,
                         unsigned &RegWidth, SmallVectorImpl<AsmToken> &Tokens);
   bool ParseRegRange(unsigned& Num, unsigned& Width);
-  unsigned getRegularReg(RegisterKind RegKind,
-                         unsigned RegNum,
-                         unsigned RegWidth,
-                         SMLoc Loc);
+  unsigned getRegularReg(RegisterKind RegKind, unsigned RegNum,
+                         unsigned RegWidth, RegisterSuffix Suffix, SMLoc Loc);
 
   bool isRegister();
   bool isRegister(const AsmToken &Token, const AsmToken &NextToken) const;
@@ -2303,7 +2303,17 @@ bool AMDGPUOperand::isInlineValue() const {
 // AsmParser
 //===----------------------------------------------------------------------===//
 
-static int getRegClass(RegisterKind Is, unsigned RegWidth) {
+static int getRegClass(RegisterKind Is, unsigned RegWidth,
+                       RegisterSuffix Suffix) {
+  if (Suffix != RegisterSuffix::None) {
+    if (Is == IS_VGPR && RegWidth == 16) {
+      if (Suffix == RegisterSuffix::Lo)
+        return AMDGPU::VGPR_LO16RegClassID;
+      assert(Suffix == RegisterSuffix::Hi);
+      return AMDGPU::VGPR_HI16RegClassID;
+    }
+    return -1;
+  }
   if (Is == IS_VGPR) {
     switch (RegWidth) {
       default: return -1;
@@ -2590,8 +2600,10 @@ AMDGPUAsmParser::isRegister(const AsmToken &Token,
     StringRef RegName = Reg->Name;
     StringRef RegSuffix = Str.substr(RegName.size());
     if (!RegSuffix.empty()) {
-      unsigned Num;
+      RegSuffix.consume_back(".l");
+      RegSuffix.consume_back(".h");
       // A single register with an index: rXX
+      unsigned Num;
       if (getRegNum(RegSuffix, Num))
         return true;
     } else {
@@ -2610,12 +2622,9 @@ AMDGPUAsmParser::isRegister()
   return isRegister(getToken(), peekToken());
 }
 
-unsigned
-AMDGPUAsmParser::getRegularReg(RegisterKind RegKind,
-                               unsigned RegNum,
-                               unsigned RegWidth,
-                               SMLoc Loc) {
-
+unsigned AMDGPUAsmParser::getRegularReg(RegisterKind RegKind, unsigned RegNum,
+                                        unsigned RegWidth,
+                                        RegisterSuffix Suffix, SMLoc Loc) {
   assert(isRegularReg(RegKind));
 
   unsigned AlignSize = 1;
@@ -2631,7 +2640,7 @@ AMDGPUAsmParser::getRegularReg(RegisterKind RegKind,
   }
 
   unsigned RegIdx = RegNum / AlignSize;
-  int RCID = getRegClass(RegKind, RegWidth);
+  int RCID = getRegClass(RegKind, RegWidth, Suffix);
   if (RCID == -1) {
     Error(Loc, "invalid or unsupported register size");
     return AMDGPU::NoRegister;
@@ -2722,20 +2731,30 @@ unsigned AMDGPUAsmParser::ParseRegularReg(RegisterKind &RegKind,
 
   RegKind = RI->Kind;
   StringRef RegSuffix = RegName.substr(RI->Name.size());
+  RegisterSuffix SuffixKind = RegisterSuffix::None;
   if (!RegSuffix.empty()) {
+    if (RegSuffix.consume_back(".l")) {
+      RegWidth = 16;
+      SuffixKind = RegisterSuffix::Lo;
+    } else if (RegSuffix.consume_back(".h")) {
+      RegWidth = 16;
+      SuffixKind = RegisterSuffix::Hi;
+    } else {
+      RegWidth = 32;
+    }
+
     // Single 32-bit register: vXX.
     if (!getRegNum(RegSuffix, RegNum)) {
       Error(Loc, "invalid register index");
       return AMDGPU::NoRegister;
     }
-    RegWidth = 32;
   } else {
     // Range of registers: v[XX:YY]. ":YY" is optional.
     if (!ParseRegRange(RegNum, RegWidth))
       return AMDGPU::NoRegister;
   }
 
-  return getRegularReg(RegKind, RegNum, RegWidth, Loc);
+  return getRegularReg(RegKind, RegNum, RegWidth, SuffixKind, Loc);
 }
 
 unsigned AMDGPUAsmParser::ParseRegList(RegisterKind &RegKind, unsigned &RegNum,
@@ -2786,8 +2805,10 @@ unsigned AMDGPUAsmParser::ParseRegList(RegisterKind &RegKind, unsigned &RegNum,
     return AMDGPU::NoRegister;
   }
 
-  if (isRegularReg(RegKind))
-    Reg = getRegularReg(RegKind, RegNum, RegWidth, ListLoc);
+  if (isRegularReg(RegKind)) {
+    Reg =
+        getRegularReg(RegKind, RegNum, RegWidth, RegisterSuffix::None, ListLoc);
+  }
 
   return Reg;
 }
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index c4baabcd9232b56..a55935e25026559 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -5250,10 +5250,15 @@ unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) const {
   case AMDGPU::S_FLOOR_F32: return AMDGPU::V_FLOOR_F32_e64;
   case AMDGPU::S_TRUNC_F32: return AMDGPU::V_TRUNC_F32_e64;
   case AMDGPU::S_RNDNE_F32: return AMDGPU::V_RNDNE_F32_e64;
-  case AMDGPU::S_CEIL_F16: return AMDGPU::V_CEIL_F16_t16_e64;
-  case AMDGPU::S_FLOOR_F16: return AMDGPU::V_FLOOR_F16_t16_e64;
-  case AMDGPU::S_TRUNC_F16: return AMDGPU::V_TRUNC_F16_t16_e64;
-  case AMDGPU::S_RNDNE_F16: return AMDGPU::V_RNDNE_F16_t16_e64;
+  case AMDGPU::S_CEIL_F16:
+    return ST.useRealTrue16Insts() ? AMDGPU::V_CEIL_F16_t16_e64
+                                   : AMDGPU::V_CEIL_F16_fake16_e64;
+  case AMDGPU::S_FLOOR_F16:
+    return AMDGPU::V_FLOOR_F16_fake16_e64;
+  case AMDGPU::S_TRUNC_F16:
+    return AMDGPU::V_TRUNC_F16_fake16_e64;
+  case AMDGPU::S_RNDNE_F16:
+    return AMDGPU::V_RNDNE_F16_fake16_e64;
   case AMDGPU::S_ADD_F32: return AMDGPU::V_ADD_F32_e64;
   case AMDGPU::S_SUB_F32: return AMDGPU::V_SUB_F32_e64;
   case AMDGPU::S_MIN_F32: return AMDGPU::V_MIN_F32_e64;
@@ -7150,8 +7155,14 @@ void SIInstrInfo::moveToVALUImpl(SIInstrWorklist &Worklist,
     if (AMDGPU::getNamedOperandIdx(NewOpcode,
                                    AMDGPU::OpName::src0_modifiers) >= 0)
       NewInstr.addImm(0);
-    if (AMDGPU::getNamedOperandIdx(NewOpcode, AMDGPU::OpName::src0) >= 0)
-      NewInstr->addOperand(Inst.getOperand(1));
+    if (AMDGPU::hasNamedOperand(NewOpcode, AMDGPU::OpName::src0)) {
+      MachineOperand Src = Inst.getOperand(1);
+      if (AMDGPU::isTrue16Inst(NewOpcode) && ST.useRealTrue16Insts() &&
+          Src.isReg() && RI.isVGPR(MRI, Src.getReg()))
+        NewInstr.addReg(Src.getReg(), 0, AMDGPU::lo16);
+      else
+        NewInstr->addOperand(Src);
+    }
 
     if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
       // We are converting these to a BFE, so we need to add the missing
diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
index 53b0513c85d8864..3850f5ef477bd7d 100644
--- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
@@ -74,6 +74,7 @@ class VOP1_Real <VOP1_Pseudo ps, int EncodingFamily, string real_name = ps.Mnemo
 
   // copy relevant pseudo op flags
   let SubtargetPredicate = ps.SubtargetPredicate;
+  let OtherPredicates    = ps.OtherPredicates;
   let AsmMatchConverter  = ps.AsmMatchConverter;
   let AsmVariantName     = ps.AsmVariantName;
   let Constraints        = ps.Constraints;
@@ -151,8 +152,11 @@ multiclass VOP1Inst_t16<string opName,
   let OtherPredicates = [NotHasTrue16BitInsts, Has16BitInsts]  in {
     defm NAME : VOP1Inst<opName, P, node>;
   }
-  let OtherPredicates = [HasTrue16BitInsts] in {
-    defm _t16 : VOP1Inst<opName#"_t16", VOPProfile_Fake16<P>, node>;
+  let OtherPredicates = [UseRealTrue16Insts] in {
+    defm _t16 : VOP1Inst<opName#"_t16", VOPProfile_True16<P>, node>;
+  }
+  let OtherPredicates = [UseFakeTrue16Insts] in {
+    defm _fake16 : VOP1Inst<opName#"_fake16", VOPProfile_Fake16<P>, node>;
   }
 }
 
@@ -673,6 +677,7 @@ class VOP1_DPP<bits<8> op, VOP1_DPP_Pseudo ps, VOPProfile p = ps.Pfl, bit isDPP1
   let SchedRW = ps.SchedRW;
   let Uses = ps.Uses;
   let TRANS = ps.TRANS;
+  let OtherPredicates = ps.OtherPredicates;
 
   bits<8> vdst;
   let Inst{8-0}   = 0xfa;
@@ -694,6 +699,7 @@ class VOP1_DPP8<bits<8> op, VOP1_Pseudo ps, VOPProfile p = ps.Pfl> :
   let Defs = ps.Defs;
   let SchedRW = ps.SchedRW;
   let Uses = ps.Uses;
+  let OtherPredicates = ps.OtherPredicates;
 
   bits<8> vdst;
   let Inst{8-0}   = fi;
@@ -706,15 +712,16 @@ class VOP1_DPP8<bits<8> op, VOP1_Pseudo ps, VOPProfile p = ps.Pfl> :
 // GFX11.
 //===----------------------------------------------------------------------===//
 
-let AssemblerPredicate = isGFX11Only, DecoderNamespace = "GFX11" in {
+let AssemblerPredicate = isGFX11Only in {
   multiclass VOP1Only_Real_gfx11<bits<9> op> {
-    let IsSingle = 1 in
+    let DecoderNamespace = "GFX11", IsSingle = 1 in
       def _gfx11 :
         VOP1_Real<!cast<VOP1_Pseudo>(NAME), SIEncodingFamily.GFX11>,
         VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME).Pfl>;
   }
   multiclass VOP1_Real_e32_gfx11<bits<9> op, string opName = NAME> {
     defvar ps = !cast<VOP1_Pseudo>(opName#"_e32");
+    let DecoderNamespace = "GFX11" in
     def _e32_gfx11 :
       VOP1_Real<ps, SIEncodingFamily.GFX11>,
       VOP1e<op{7-0}, ps.Pfl>;
@@ -722,11 +729,13 @@ let AssemblerPredicate = isGFX11Only, DecoderNamespace = "GFX11" in {
   multiclass VOP1_Real_e32_with_name_gfx11<bits<9> op, string opName,
                                        string asmName> {
     defvar ps = !cast<VOP1_Pseudo>(opName#"_e32");
-    let AsmString = asmName # ps.AsmOperands in {
+    let AsmString = asmName # ps.AsmOperands,
+        DecoderNamespace = !if(ps.Pfl.IsRealTrue16, "GFX11", "GFX11_FAKE16") in {
       defm NAME : VOP1_Real_e32_gfx11<op, opName>;
     }
   }
   multiclass VOP1_Real_e64_gfx11<bits<9> op> {
+    let DecoderNamespace = "GFX11" in
     def _e64_gfx11 :
       VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX11>,
       VOP3e_gfx11<{0, 1, 1, op{6-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
@@ -740,7 +749,9 @@ let AssemblerPredicate = isGFX11Only, DecoderNamespace = "GFX11" in {
   multiclass VOP1_Real_dpp_with_name_gfx11<bits<9> op, string opName,
                                            string asmName> {
     defvar ps = !cast<VOP1_Pseudo>(opName#"_e32");
-    let AsmString = asmName # ps.Pfl.AsmDPP16, DecoderNamespace = "DPPGFX11" in {
+    let AsmString = asmName # ps.Pfl.AsmDPP16,
+        DecoderNamespace = !if(ps.Pfl.IsRealTrue16,
+                               "DPPGFX11", "DPPGFX11_FAKE16") in {
       defm NAME : VOP1_Real_dpp_gfx11<op, opName>;
     }
   }
@@ -753,11 +764,13 @@ let AssemblerPredicate = isGFX11Only, DecoderNamespace = "GFX11" in {
   multiclass VOP1_Real_dpp8_with_name_gfx11<bits<9> op, string opName,
                                            string asmName> {
     defvar ps = !cast<VOP1_Pseudo>(opName#"_e32");
-    let AsmString = asmName # ps.Pfl.AsmDPP8, DecoderNamespace = "DPP8GFX11" in {
+    let AsmString = asmName # ps.Pfl.AsmDPP8,
+        DecoderNamespace = !if(ps.Pfl.IsRealTrue16,
+                               "DPP8GFX11", "DPP8GFX11_FAKE16") in {
       defm NAME : VOP1_Real_dpp8_gfx11<op, opName>;
     }
   }
-} // End AssemblerPredicate = isGFX11Only, DecoderNamespace = "GFX11"
+} // End AssemblerPredicate = isGFX11Only
 
 multiclass VOP1_Realtriple_e64_gfx11<bits<9> op> {
   defm NAME : VOP3_Realtriple_gfx11<{0, 1, 1, op{6-0}}, /*isSingle=*/ 0, NAME>;
@@ -806,29 +819,30 @@ defm V_CLS_I32             : VOP1_Real_FULL_with_name_gfx11<0x03b,
   "V_FFBH_I32", "v_cls_i32">;
 defm V_PERMLANE64_B32      : VOP1Only_Real_gfx11<0x067>;
 defm V_MOV_B16_t16           : VOP1_Real_FULL_t16_gfx11<0x01c, "v_mov_b16">;
-defm V_NOT_B16_t16           : VOP1_Real_FULL_t16_gfx11<0x069, "v_not_b16">;
-defm V_CVT_I32_I16_t16       : VOP1_Real_FULL_t16_gfx11<0x06a, "v_cvt_i32_i16">;
-defm V_CVT_U32_U16_t16       : VOP1_Real_FULL_t16_gfx11<0x06b, "v_cvt_u32_u16">;
+defm V_NOT_B16_fake16        : VOP1_Real_FULL_t16_gfx11<0x069, "v_not_b16">;
+defm V_CVT_I32_I16_fake16    : VOP1_Real_FULL_t16_gfx11<0x06a, "v_cvt_i32_i16">;
+defm V_CVT_U32_U16_fake16    : VOP1_Real_FULL_t16_gfx11<0x06b, "v_cvt_u32_u16">;
 
 defm V_CVT_F16_U16_t16       : VOP1_Real_FULL_t16_gfx11<0x050, "v_cvt_f16_u16">;
 defm V_CVT_F16_I16_t16       : VOP1_Real_FULL_t16_gfx11<0x051, "v_cvt_f16_i16">;
 defm V_CVT_U16_F16_t16       : VOP1_Real_FULL_t16_gfx11<0x052, "v_cvt_u16_f16">;
 defm V_CVT_I16_F16_t16       : VOP1_Real_FULL_t16_gfx11<0x053, "v_cvt_i16_f16">;
-defm V_RCP_F16_t16           : VOP1_Real_FULL_t16_gfx11<0x054, "v_rcp_f16">;
-defm V_SQRT_F16_t16          : VOP1_Real_FULL_t16_gfx11<0x055, "v_sqrt_f16">;
-defm V_RSQ_F16_t16           : VOP1_Real_FULL_t16_gfx11<0x056, "v_rsq_f16">;
-defm V_LOG_F16_t16           : VOP1_Real_FULL_t16_gfx11<0x057, "v_log_f16">;
-defm V_EXP_F16_t16           : VOP1_Real_FULL_t16_gfx11<0x058, "v_exp_f16">;
-defm V_FREXP_MANT_F16_t16    : VOP1_Real_FULL_t16_gfx11<0x059, "v_frexp_mant_f16">;
+defm V_RCP_F16_fake16        : VOP1_Real_FULL_t16_gfx11<0x054, "v_rcp_f16">;
+defm V_SQRT_F16_fake16       : VOP1_Real_FULL_t16_gfx11<0x055, "v_sqrt_f16">;
+defm V_RSQ_F16_fake16        : VOP1_Real_FULL_t16_gfx11<0x056, "v_rsq_f16">;
+defm V_LOG_F16_fake16        : VOP1_Real_FULL_t16_gfx11<0x057, "v_log_f16">;
+defm V_EXP_F16_fake16        : VOP1_Real_FULL_t16_gfx11<0x058, "v_exp_f16">;
+defm V_FREXP_MANT_F16_fake16 : VOP1_Real_FULL_t16_gfx11<0x059, "v_frexp_mant_f16">;
 defm V_FREXP_EXP_I16_F16_t16 : VOP1_Real_FULL_t16_gfx11<0x05a, "v_frexp_exp_i16_f16">;
-defm V_FLOOR_F16_t16         : VOP1_Real_FULL_t16_gfx11<0x05b, "v_floor_f16">;
+defm V_FLOOR_F16_fake16      : VOP1_Real_FULL_t16_gfx11<0x05b, "v_floor_f16">;
 defm V_CEIL_F16_t16          : VOP1_Real_FULL_t16_gfx11<0x05c, "v_ceil_f16">;
-defm V_TRUNC_F16_t16         : VOP1_Real_FULL_t16_gfx11<0x05d, "v_trunc_f16">;
-defm V_RNDNE_F16_t16         : VOP1_Real_FULL_t16_gfx11<0x05e, "v_rndne_f16">;
-defm V_FRACT_F16_t16         : VOP1_Real_FULL_t16_gfx11<0x05f, "v_fract_f16">;
-defm V_SIN_F16_t16           : VOP1_Real_FULL_t16_gfx11<0x060, "v_sin_f16">;
-defm V_COS_F16_t16           : VOP1_Real_FULL_t16_gfx11<0x061, "v_cos_f16">;
-defm V_SAT_PK_U8_I16_t16     : VOP1_Real_FULL_t16_gfx11<0x062, "v_sat_pk_u8_i16">;
+defm V_CEIL_F16_fake16       : VOP1_Real_FULL_t16_gfx11<0x05c, "v_ceil_f16">;
+defm V_TRUNC_F16_fake16      : VOP1_Real_FULL_t16_gfx11<0x05d, "v_trunc_f16">;
+defm V_RNDNE_F16_fake16      : VOP1_Real_FULL_t16_gfx11<0x05e, "v_rndne_f16">;
+defm V_FRACT_F16_fake16      : VOP1_Real_FULL_t16_gfx11<0x05f, "v_fract_f16">;
+defm V_SIN_F16_fake16        : VOP1_Real_FULL_t16_gfx11<0x060, "v_sin_f16">;
+defm V_COS_F16_fake16        : VOP1_Real_FULL_t16_gfx11<0x061, "v_cos_f16">;
+defm V_SAT_PK_U8_I16_fake16  : VOP1_Real_FULL_t16_gfx11<0x062, "v_sat_pk_u8_i16">;
 defm V_CVT_NORM_I16_F16_t16  : VOP1_Real_FULL_t16_gfx11<0x063, "v_cvt_norm_i16_f16">;
 defm V_CVT_NORM_U16_F16_t16  : VOP1_Real_FULL_t16_gfx11<0x064, "v_cvt_norm_u16_f16">;
 
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir
index 70ed03376ae49b9..a270dffe7b595f7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir
@@ -48,16 +48,19 @@ body: |
     ; GFX11-LABEL: name: fceil_s16_vv
     ; GFX11: liveins: $vgpr0
     ; GFX11-NEXT: {{  $}}
-    ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; GFX11-NEXT: [[V_CEIL_F16_t16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CEIL_F16_t16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
-    ; GFX11-NEXT: $vgpr0 = COPY [[V_CEIL_F16_t16_e64_]]
+    ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
+    ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:vgpr_16(s16) = G_TRUNC [[COPY]](s32)
+    ; GFX11-NEXT: [[V_CEIL_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_CEIL_F16_t16_e64 0, [[TRUNC]](s16), 0, 0, implicit $mode, implicit $exec
+    ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s16) = COPY [[V_CEIL_F16_t16_e64_]]
+    ; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY [[COPY1]](s16)
+    ; GFX11-NEXT: $vgpr0 = COPY [[COPY2]](s32)
     ;
     ; GFX11-FAKE16-LABEL: name: fceil_s16_vv
     ; GFX11-FAKE16: liveins: $vgpr0
     ; GFX11-FAKE16-NEXT: {{  $}}
     ; GFX11-FAKE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; GFX11-FAKE16-NEXT: [[V_CEIL_F16_t16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CEIL_F16_t16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
-    ; GFX11-FAKE16-NEXT: $vgpr0 = COPY [[V_CEIL_F16_t16_e64_]]
+    ; GFX11-FAKE16-NEXT: [[V_CEIL_F16_fake16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CEIL_F16_fake16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
+    ; GFX11-FAKE16-NEXT: $vgpr0 = COPY [[V_CEIL_F16_fake16_e64_]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s16) = G_TRUNC %0
     %2:vgpr(s16) = G_FCEIL %1
@@ -86,15 +89,16 @@ body: |
     ; GFX11: liveins: $sgpr0
     ; GFX11-NEXT: {{  $}}
     ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; GFX11-NEXT: [[V_CEIL_F16_t16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CEIL_F16_t16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
-    ; GFX11-NEXT: $vgpr0 = COPY [[V_CEIL_F16_t16_e64_]]
+    ; GFX11-NEXT: [[V_CEIL_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_CEIL_F16_t16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
+    ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[V_CEIL_F16_t16_e64_]]
+    ; GFX11-NEXT: $vgpr0 = COPY [[COPY1]]
     ;
     ; GFX11-FAKE16-LABEL: name: fceil_s16_vs
     ; GFX11-FAKE16: liveins: $sgpr0
     ; GFX11-FAKE16-NEXT: {{  $}}
     ; GFX11-FAKE16-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; GFX11-FAKE16-NEXT: [[V_CEIL_F16_t16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CEIL_F16_t16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
-    ; GFX11-FAKE16-NEXT: $vgpr0 = COPY [[V_CEIL_F16_t16_e64_]]
+    ; GFX11-FAKE16-NEXT: [[V_CEIL_F16_fake16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CEIL_F16_fake16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
+    ; GFX11-FAKE16-NEXT: $vgpr0 = COPY [[V_CEIL_F16_fake16_e64_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s16) = G_TRUNC %0
     %2:vgpr(s16) = G_FCEIL %1
@@ -122,16 +126,19 @@ body: |
     ; GFX11-LABEL: name: fceil_fneg_s16_vv
     ; GFX11: liveins: $vgpr0
     ; GFX11-NEXT: {{  $}}
-    ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; GFX11-NEXT: [[V_CEIL_F16_t16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CEIL_F16_t16_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec
-    ; GFX11-NEXT: $vgpr0 = COPY [[V_CEIL_F16_t16_e64_]]
+    ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
+    ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:vgpr_16(s16) = G_TRUNC [[COPY]](s32)
+    ; GFX11-NEXT: [[V_CEIL_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_CEIL_F16_t16_e64 1, [[TRUNC]](s16), 0, 0, implicit $mode, implicit $exec
+    ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s16) = COPY [[V_CEIL_F16_t16_e64_]]
+    ; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY [[COPY1]](s16)
+    ; GFX11-NEXT: $vgpr0 = COPY [[COPY2]](s32)
     ;
     ; GFX11-FAKE16-LABEL: name: fceil_fneg_s16_vv
     ; GFX11-FAKE16: liveins: $vgpr0
     ; GFX11-FAKE16-NEXT: {{  $}}
     ; GFX11-FAKE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; GFX11-FAKE16-NEXT: [[V_CEIL_F16_t16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CEIL_F16_t16_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec
-    ; GFX11-FAKE16-NEXT: $vgpr0 = COPY [[V_CEIL_F16_t16_e64_]]
+    ; GFX11-FAKE16-NEXT: [[V_CEIL_F16_fake16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CEIL_F16_fake16_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec
+    ; GFX11-FAKE16-NEXT: $vgpr0 = COPY [[V_CEIL_F16_fake16_e64_]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s16) = G_TRUNC %0
     %2:vgpr(s16) = G_FNEG %1
diff --git a/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16.mir b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16.mir
index a8f7a66d9b71aa2..c2e95501d7fd977 100644
--- a/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16.mir
+++ b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16.mir
@@ -1,6 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
-# RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN %s
-# RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN %s
+# RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN,REAL16 %s
+# RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN,FAKE16 %s
 
 ---
 name:            cmp_f16
@@ -62,11 +62,17 @@ body:             |
 name:            ceil_f16
 body:             |
   bb.0:
-    ; GCN-LABEL: name: ceil_f16
-    ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
-    ; GCN-NEXT: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[DEF]], 0, 0, implicit $mode, implicit $exec
-    ; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
-    ; GCN-NEXT: [[V_CEIL_F16_t16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CEIL_F16_t16_e64 0, [[V_CVT_F32_U32_e64_]], 0, 0, implicit $mode, implicit $exec
+    ; REAL16-LABEL: name: ceil_f16
+    ; REAL16: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+    ; REAL16-NEXT: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[DEF]], 0, 0, implicit $mode, implicit $exec
+    ; REAL16-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+    ; REAL16-NEXT: [[V_CEIL_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_CEIL_F16_t16_e64 0, [[V_CVT_F32_U32_e64_]].lo16, 0, 0, implicit $mode, implicit $exec
+    ;
+    ; FAKE16-LABEL: name: ceil_f16
+    ; FAKE16: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+    ; FAKE16-NEXT: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[DEF]], 0, 0, implicit $mode, implicit $exec
+    ; FAKE16-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+    ; FAKE16-NEXT: [[V_CEIL_F16_fake16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CEIL_F16_fake16_e64 0, [[V_CVT_F32_U32_e64_]], 0, 0, implicit $mode, implicit $exec
     %0:vgpr_32 = IMPLICIT_DEF
     %1:vgpr_32 = V_CVT_F32_U32_e64 %0:vgpr_32, 0, 0, implicit $mode, implicit $exec
     %2:sreg_32 = COPY %1:vgpr_32
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
index 41b9426eba26732..2afcec072695bdd 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
@@ -60,7 +60,7 @@ define amdgpu_kernel void @ceil_f16(
 ; GFX11-NEXT:    buffer_load_u16 v0, off, s[8:11], 0
 ; GFX11-NEXT:    s_mov_b32 s5, s1
 ; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_ceil_f16_e32 v0, v0
+; GFX11-NEXT:    v_ceil_f16_e32 v0.l, v0.l
 ; GFX11-NEXT:    buffer_store_b16 v0, off, s[4:7], 0
 ; GFX11-NEXT:    s_nop 0
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
@@ -163,10 +163,13 @@ define amdgpu_kernel void @ceil_v2f16(
 ; GFX11-NEXT:    s_mov_b32 s5, s1
 ; GFX11-NEXT:    s_waitcnt vmcnt(0)
 ; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-NEXT:    v_ceil_f16_e32 v0, v0
+; GFX11-NEXT:    v_ceil_f16_e32 v0.l, v0.l
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT:    v_ceil_f16_e32 v0.h, v1.l
+; GFX11-NEXT:    v_mov_b16_e32 v1.l, v0.l
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_ceil_f16_e32 v1, v1
-; GFX11-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-NEXT:    v_pack_b32_f16 v0, v1, v0
 ; GFX11-NEXT:    buffer_store_b32 v0, off, s[4:7], 0
 ; GFX11-NEXT:    s_nop 0
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop1.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop1.s
index 0aeb9b35ff378cb..6b19a5c94a64e4d 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop1.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop1.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
-// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16,+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16,-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
 
 v_bfrev_b32_e32 v5, v1
 // GFX11: encoding: [0x01,0x71,0x0a,0x7e]
@@ -46,50 +46,56 @@ v_bfrev_b32 v5, src_scc
 v_bfrev_b32 v255, 0xaf123456
 // GFX11: encoding: [0xff,0x70,0xfe,0x7f,0x56,0x34,0x12,0xaf]
 
-v_ceil_f16 v5, v1
+v_ceil_f16 v5.l, v1.l
 // GFX11: encoding: [0x01,0xb9,0x0a,0x7e]
 
-v_ceil_f16 v5, v127
+v_ceil_f16 v5.l, v127.l
 // GFX11: encoding: [0x7f,0xb9,0x0a,0x7e]
 
-v_ceil_f16 v5, s1
+v_ceil_f16 v5.l, v1.h
+// GFX11: encoding: [0x81,0xb9,0x0a,0x7e]
+
+v_ceil_f16 v5.l, v127.h
+// GFX11: encoding: [0xff,0xb9,0x0a,0x7e]
+
+v_ceil_f16 v5.l, s1
 // GFX11: encoding: [0x01,0xb8,0x0a,0x7e]
 
-v_ceil_f16 v5, s105
+v_ceil_f16 v5.l, s105
 // GFX11: encoding: [0x69,0xb8,0x0a,0x7e]
 
-v_ceil_f16 v5, vcc_lo
+v_ceil_f16 v5.l, vcc_lo
 // GFX11: encoding: [0x6a,0xb8,0x0a,0x7e]
 
-v_ceil_f16 v5, vcc_hi
+v_ceil_f16 v5.l, vcc_hi
 // GFX11: encoding: [0x6b,0xb8,0x0a,0x7e]
 
-v_ceil_f16 v5, ttmp15
+v_ceil_f16 v5.l, ttmp15
 // GFX11: encoding: [0x7b,0xb8,0x0a,0x7e]
 
-v_ceil_f16 v5, m0
+v_ceil_f16 v5.l, m0
 // GFX11: encoding: [0x7d,0xb8,0x0a,0x7e]
 
-v_ceil_f16 v5, exec_lo
+v_ceil_f16 v5.l, exec_lo
 // GFX11: encoding: [0x7e,0xb8,0x0a,0x7e]
 
-v_ceil_f16 v5, exec_hi
+v_ceil_f16 v5.l, exec_hi
 // GFX11: encoding: [0x7f,0xb8,0x0a,0x7e]
 
-v_ceil_f16 v5, null
+v_ceil_f16 v5.l, null
 // GFX11: encoding: [0x7c,0xb8,0x0a,0x7e]
 
-v_ceil_f16 v5, -1
+v_ceil_f16 v5.l, -1
 // GFX11: encoding: [0xc1,0xb8,0x0a,0x7e]
 
-v_ceil_f16 v5, 0.5
-// GFX11: encoding: [0xf0,0xb8,0x0a,0x7e]
+v_ceil_f16 v127.l, 0.5
+// GFX11: encoding: [0xf0,0xb8,0xfe,0x7e]
 
-v_ceil_f16 v5, src_scc
-// GFX11: encoding: [0xfd,0xb8,0x0a,0x7e]
+v_ceil_f16 v5.h, src_scc
+// GFX11: encoding: [0xfd,0xb8,0x0a,0x7f]
 
-v_ceil_f16 v127, 0xfe0b
-// GFX11: encoding: [0xff,0xb8,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+v_ceil_f16 v127.h, 0xfe0b
+// GFX11: encoding: [0xff,0xb8,0xfe,0x7f,0x0b,0xfe,0x00,0x00]
 
 v_ceil_f32 v5, v1
 // GFX11: encoding: [0x01,0x45,0x0a,0x7e]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16.s
index 8c6873e2cbe3228..cd9aa9273f1d866 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
-// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16,+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16,-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
 
 v_bfrev_b32_dpp v5, v1 quad_perm:[3,2,1,0]
 // GFX11: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x1b,0x00,0xff]
@@ -43,47 +43,47 @@ v_bfrev_b32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
 v_bfrev_b32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
 // GFX11: encoding: [0xfa,0x70,0xfe,0x7f,0xff,0x6f,0x05,0x30]
 
-v_ceil_f16 v5, v1 quad_perm:[3,2,1,0]
+v_ceil_f16 v5.l, v1 quad_perm:[3,2,1,0]
 // GFX11: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x1b,0x00,0xff]
 
-v_ceil_f16 v5, v1 quad_perm:[0,1,2,3]
+v_ceil_f16 v5.l, v1 quad_perm:[0,1,2,3]
 // GFX11: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x00,0xff]
 
-v_ceil_f16 v5, v1 row_mirror
+v_ceil_f16 v5.l, v1 row_mirror
 // GFX11: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x40,0x01,0xff]
 
-v_ceil_f16 v5, v1 row_half_mirror
+v_ceil_f16 v5.l, v1 row_half_mirror
 // GFX11: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x41,0x01,0xff]
 
-v_ceil_f16 v5, v1 row_shl:1
+v_ceil_f16 v5.l, v1 row_shl:1
 // GFX11: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x01,0x01,0xff]
 
-v_ceil_f16 v5, v1 row_shl:15
+v_ceil_f16 v5.l, v1 row_shl:15
 // GFX11: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x0f,0x01,0xff]
 
-v_ceil_f16 v5, v1 row_shr:1
+v_ceil_f16 v5.l, v1 row_shr:1
 // GFX11: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x11,0x01,0xff]
 
-v_ceil_f16 v5, v1 row_shr:15
+v_ceil_f16 v5.l, v1 row_shr:15
 // GFX11: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x1f,0x01,0xff]
 
-v_ceil_f16 v5, v1 row_ror:1
+v_ceil_f16 v5.l, v1 row_ror:1
 // GFX11: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x21,0x01,0xff]
 
-v_ceil_f16 v5, v1 row_ror:15
+v_ceil_f16 v5.l, v1 row_ror:15
 // GFX11: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x2f,0x01,0xff]
 
-v_ceil_f16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+v_ceil_f16 v5.l, v1 row_share:0 row_mask:0xf bank_mask:0xf
 // GFX11: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x50,0x01,0xff]
 
-v_ceil_f16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
-// GFX11: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+v_ceil_f16 v127.l, v127 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX11: encoding: [0xfa,0xb8,0xfe,0x7e,0x7f,0x5f,0x01,0x01]
 
-v_ceil_f16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
-// GFX11: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x60,0x09,0x13]
+v_ceil_f16 v5.h, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX11: encoding: [0xfa,0xb8,0x0a,0x7f,0x01,0x60,0x09,0x13]
 
-v_ceil_f16 v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
-// GFX11: encoding: [0xfa,0xb8,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
+v_ceil_f16 v127.h, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX11: encoding: [0xfa,0xb8,0xfe,0x7f,0x7f,0x6f,0x35,0x30]
 
 v_ceil_f32 v5, v1 quad_perm:[3,2,1,0]
 // GFX11: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp8.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp8.s
index a765d333db2b74d..1633e5115efbeb3 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp8.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp8.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
-// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16,+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16,-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
 
 v_bfrev_b32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
 // GFX11: encoding: [0xe9,0x70,0x0a,0x7e,0x01,0x77,0x39,0x05]
@@ -10,14 +10,17 @@ v_bfrev_b32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
 v_bfrev_b32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
 // GFX11: encoding: [0xe9,0x70,0xfe,0x7f,0xff,0x00,0x00,0x00]
 
-v_ceil_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+v_ceil_f16 v5.l, v1 dpp8:[7,6,5,4,3,2,1,0]
 // GFX11: encoding: [0xe9,0xb8,0x0a,0x7e,0x01,0x77,0x39,0x05]
 
-v_ceil_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
-// GFX11: encoding: [0xea,0xb8,0x0a,0x7e,0x01,0x77,0x39,0x05]
+v_ceil_f16 v127.l, v127 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0xe9,0xb8,0xfe,0x7e,0x7f,0x77,0x39,0x05]
 
-v_ceil_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
-// GFX11: encoding: [0xe9,0xb8,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+v_ceil_f16 v5.h, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX11: encoding: [0xea,0xb8,0x0a,0x7f,0x01,0x77,0x39,0x05]
+
+v_ceil_f16 v127.h, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX11: encoding: [0xe9,0xb8,0xfe,0x7f,0x7f,0x00,0x00,0x00]
 
 v_ceil_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
 // GFX11: encoding: [0xe9,0x44,0x0a,0x7e,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
index 1f350ae6863849e..b2ebc3d26549b2c 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
@@ -1,14 +1,23 @@
-// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
-// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16,+wavefrontsize32,-wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16,-wavefrontsize32,+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
 
-v_ceil_f16_e32 v128, 0xfe0b
-// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+v_ceil_f16_e32 v128.l, 0xfe0b
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 
-v_ceil_f16_e32 v255, v1
-// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+v_ceil_f16_e32 v128.h, 0xfe0b
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 
-v_ceil_f16_e32 v5, v199
-// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+v_ceil_f16_e32 v255.l, v1.l
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_ceil_f16_e32 v255.h, v1.h
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_ceil_f16_e32 v5.l, v199.l
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_ceil_f16_e32 v5.h, v199.h
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 
 v_cos_f16_e32 v128, 0xfe0b
 // GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
@@ -211,10 +220,16 @@ v_trunc_f16_e32 v255, v1
 v_trunc_f16_e32 v5, v199
 // GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 
-v_ceil_f16_e32 v255, v1 quad_perm:[3,2,1,0]
+v_ceil_f16_e32 v255.l, v1.l quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_ceil_f16_e32 v255.h, v1.h quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_ceil_f16_e32 v5.l, v199.l quad_perm:[3,2,1,0]
 // GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 
-v_ceil_f16_e32 v5, v199 quad_perm:[3,2,1,0]
+v_ceil_f16_e32 v5.h, v199.h quad_perm:[3,2,1,0]
 // GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 
 v_cos_f16_e32 v255, v1 quad_perm:[3,2,1,0]
@@ -358,10 +373,16 @@ v_trunc_f16_e32 v255, v1 quad_perm:[3,2,1,0]
 v_trunc_f16_e32 v5, v199 quad_perm:[3,2,1,0]
 // GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 
-v_ceil_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+v_ceil_f16_e32 v255.l, v1.l dpp8:[7,6,5,4,3,2,1,0]
 // GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 
-v_ceil_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+v_ceil_f16_e32 v255.h, v1.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_ceil_f16_e32 v5.l, v199.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_ceil_f16_e32 v5.h, v199.h dpp8:[7,6,5,4,3,2,1,0]
 // GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 
 v_cos_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
@@ -504,4 +525,3 @@ v_trunc_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
 
 v_trunc_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
 // GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-
diff --git a/llvm/test/MC/AMDGPU/gfx11_unsupported_sdwa.s b/llvm/test/MC/AMDGPU/gfx11_unsupported_sdwa.s
index 9ca3861eb93600b..1121f394b3d2685 100644
--- a/llvm/test/MC/AMDGPU/gfx11_unsupported_sdwa.s
+++ b/llvm/test/MC/AMDGPU/gfx11_unsupported_sdwa.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
-// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16,+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16,-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
 
 v_add_co_ci_u32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported
@@ -28,7 +28,7 @@ v_ashrrev_i32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWO
 v_bfrev_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported
 
-v_ceil_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+v_ceil_f16_sdwa v255.l, v1.l dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported
 
 v_ceil_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1.txt
index 7156fb19d2bb052..b8efe4b1e562329 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1.txt
@@ -1,5 +1,7 @@
-# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
-# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,GFX11-REAL16 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16,-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-real-true16,-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
 
 # GFX11: v_bfrev_b32_e32 v5, v1                  ; encoding: [0x01,0x71,0x0a,0x7e]
 0x01,0x71,0x0a,0x7e
@@ -46,50 +48,73 @@
 # GFX11: v_bfrev_b32_e32 v255, 0xaf123456        ; encoding: [0xff,0x70,0xfe,0x7f,0x56,0x34,0x12,0xaf]
 0xff,0x70,0xfe,0x7f,0x56,0x34,0x12,0xaf
 
-# GFX11: v_ceil_f16_e32 v5, v1                   ; encoding: [0x01,0xb9,0x0a,0x7e]
+# GFX11-FAKE16: v_ceil_f16_e32 v5, v1            ; encoding: [0x01,0xb9,0x0a,0x7e]
+# GFX11-REAL16: v_ceil_f16_e32 v5.l, v1.l        ; encoding: [0x01,0xb9,0x0a,0x7e]
 0x01,0xb9,0x0a,0x7e
 
-# GFX11: v_ceil_f16_e32 v5, v127                 ; encoding: [0x7f,0xb9,0x0a,0x7e]
+# GFX11-FAKE16: v_ceil_f16_e32 v5, v127          ; encoding: [0x7f,0xb9,0x0a,0x7e]
+# GFX11-REAL16: v_ceil_f16_e32 v5.l, v127.l      ; encoding: [0x7f,0xb9,0x0a,0x7e]
 0x7f,0xb9,0x0a,0x7e
 
-# GFX11: v_ceil_f16_e32 v5, s1                   ; encoding: [0x01,0xb8,0x0a,0x7e]
+# GFX11-FAKE16: v_ceil_f16_e32 v5, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/ ; encoding: [0x81,0xb9,0x0a,0x7e]
+# GFX11-REAL16: v_ceil_f16_e32 v5.l, v1.h        ; encoding: [0x81,0xb9,0x0a,0x7e]
+0x81,0xb9,0x0a,0x7e
+
+# GFX11-FAKE16: v_ceil_f16_e32 v5, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/ ; encoding: [0xff,0xb9,0x0a,0x7e]
+# GFX11-REAL16: v_ceil_f16_e32 v5.l, v127.h      ; encoding: [0xff,0xb9,0x0a,0x7e]
+0xff,0xb9,0x0a,0x7e
+
+# GFX11-FAKE16: v_ceil_f16_e32 v5, s1            ; encoding: [0x01,0xb8,0x0a,0x7e]
+# GFX11-REAL16: v_ceil_f16_e32 v5.l, s1          ; encoding: [0x01,0xb8,0x0a,0x7e]
 0x01,0xb8,0x0a,0x7e
 
-# GFX11: v_ceil_f16_e32 v5, s105                 ; encoding: [0x69,0xb8,0x0a,0x7e]
+# GFX11-FAKE16: v_ceil_f16_e32 v5, s105          ; encoding: [0x69,0xb8,0x0a,0x7e]
+# GFX11-REAL16: v_ceil_f16_e32 v5.l, s105        ; encoding: [0x69,0xb8,0x0a,0x7e]
 0x69,0xb8,0x0a,0x7e
 
-# GFX11: v_ceil_f16_e32 v5, vcc_lo               ; encoding: [0x6a,0xb8,0x0a,0x7e]
+# GFX11-FAKE16: v_ceil_f16_e32 v5, vcc_lo        ; encoding: [0x6a,0xb8,0x0a,0x7e]
+# GFX11-REAL16: v_ceil_f16_e32 v5.l, vcc_lo      ; encoding: [0x6a,0xb8,0x0a,0x7e]
 0x6a,0xb8,0x0a,0x7e
 
-# GFX11: v_ceil_f16_e32 v5, vcc_hi               ; encoding: [0x6b,0xb8,0x0a,0x7e]
+# GFX11-FAKE16: v_ceil_f16_e32 v5, vcc_hi        ; encoding: [0x6b,0xb8,0x0a,0x7e]
+# GFX11-REAL16: v_ceil_f16_e32 v5.l, vcc_hi      ; encoding: [0x6b,0xb8,0x0a,0x7e]
 0x6b,0xb8,0x0a,0x7e
 
-# GFX11: v_ceil_f16_e32 v5, ttmp15               ; encoding: [0x7b,0xb8,0x0a,0x7e]
+# GFX11-FAKE16: v_ceil_f16_e32 v5, ttmp15        ; encoding: [0x7b,0xb8,0x0a,0x7e]
+# GFX11-REAL16: v_ceil_f16_e32 v5.l, ttmp15      ; encoding: [0x7b,0xb8,0x0a,0x7e]
 0x7b,0xb8,0x0a,0x7e
 
-# GFX11: v_ceil_f16_e32 v5, m0                   ; encoding: [0x7d,0xb8,0x0a,0x7e]
+# GFX11-FAKE16: v_ceil_f16_e32 v5, m0            ; encoding: [0x7d,0xb8,0x0a,0x7e]
+# GFX11-REAL16: v_ceil_f16_e32 v5.l, m0          ; encoding: [0x7d,0xb8,0x0a,0x7e]
 0x7d,0xb8,0x0a,0x7e
 
-# GFX11: v_ceil_f16_e32 v5, exec_lo              ; encoding: [0x7e,0xb8,0x0a,0x7e]
+# GFX11-FAKE16: v_ceil_f16_e32 v5, exec_lo       ; encoding: [0x7e,0xb8,0x0a,0x7e]
+# GFX11-REAL16: v_ceil_f16_e32 v5.l, exec_lo     ; encoding: [0x7e,0xb8,0x0a,0x7e]
 0x7e,0xb8,0x0a,0x7e
 
-# GFX11: v_ceil_f16_e32 v5, exec_hi              ; encoding: [0x7f,0xb8,0x0a,0x7e]
+# GFX11-FAKE16: v_ceil_f16_e32 v5, exec_hi       ; encoding: [0x7f,0xb8,0x0a,0x7e]
+# GFX11-REAL16: v_ceil_f16_e32 v5.l, exec_hi     ; encoding: [0x7f,0xb8,0x0a,0x7e]
 0x7f,0xb8,0x0a,0x7e
 
-# GFX11: v_ceil_f16_e32 v5, null                 ; encoding: [0x7c,0xb8,0x0a,0x7e]
+# GFX11-FAKE16: v_ceil_f16_e32 v5, null          ; encoding: [0x7c,0xb8,0x0a,0x7e]
+# GFX11-REAL16: v_ceil_f16_e32 v5.l, null        ; encoding: [0x7c,0xb8,0x0a,0x7e]
 0x7c,0xb8,0x0a,0x7e
 
-# GFX11: v_ceil_f16_e32 v5, -1                   ; encoding: [0xc1,0xb8,0x0a,0x7e]
+# GFX11-FAKE16: v_ceil_f16_e32 v5, -1            ; encoding: [0xc1,0xb8,0x0a,0x7e]
+# GFX11-REAL16: v_ceil_f16_e32 v5.l, -1          ; encoding: [0xc1,0xb8,0x0a,0x7e]
 0xc1,0xb8,0x0a,0x7e
 
-# GFX11: v_ceil_f16_e32 v5, 0.5                  ; encoding: [0xf0,0xb8,0x0a,0x7e]
-0xf0,0xb8,0x0a,0x7e
+# GFX11-FAKE16: v_ceil_f16_e32 v127, 0.5         ; encoding: [0xf0,0xb8,0xfe,0x7e]
+# GFX11-REAL16: v_ceil_f16_e32 v127.l, 0.5       ; encoding: [0xf0,0xb8,0xfe,0x7e]
+0xf0,0xb8,0xfe,0x7e
 
-# GFX11: v_ceil_f16_e32 v5, src_scc              ; encoding: [0xfd,0xb8,0x0a,0x7e]
-0xfd,0xb8,0x0a,0x7e
+# COM: GFX11-FAKE16: warning: invalid instruction encoding 0xfd,0xb8,0x0a,0x7f
+# GFX11-REAL16: v_ceil_f16_e32 v5.h, src_scc     ; encoding: [0xfd,0xb8,0x0a,0x7f]
+0xfd,0xb8,0x0a,0x7f
 
-# GFX11: v_ceil_f16_e32 v127, 0xfe0b             ; encoding: [0xff,0xb8,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
-0xff,0xb8,0xfe,0x7e,0x0b,0xfe,0x00,0x00
+# COM: GFX11-FAKE16: warning: invalid instruction encoding 0xff,0xb8,0xfe,0x7f,0x0b,0xfe,0x00,0x00
+# GFX11-REAL16: v_ceil_f16_e32 v127.h, 0xfe0b    ; encoding: [0xff,0xb8,0xfe,0x7f,0x0b,0xfe,0x00,0x00]
+0xff,0xb8,0xfe,0x7f,0x0b,0xfe,0x00,0x00
 
 # GFX11: v_ceil_f32_e32 v5, v1                   ; encoding: [0x01,0x45,0x0a,0x7e]
 0x01,0x45,0x0a,0x7e



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