[llvm] 5169100 - [NFC][X86] Clang-format X86FrameLowering.cpp (#73287)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 23 22:12:25 PST 2023
Author: Shengchen Kan
Date: 2023-11-24T14:12:20+08:00
New Revision: 5169100ecddadb35e3537c74d5b15fad5b6d86d1
URL: https://github.com/llvm/llvm-project/commit/5169100ecddadb35e3537c74d5b15fad5b6d86d1
DIFF: https://github.com/llvm/llvm-project/commit/5169100ecddadb35e3537c74d5b15fad5b6d86d1.diff
LOG: [NFC][X86] Clang-format X86FrameLowering.cpp (#73287)
Added:
Modified:
llvm/lib/Target/X86/X86FrameLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86FrameLowering.cpp b/llvm/lib/Target/X86/X86FrameLowering.cpp
index f268fd5b3fe95e6..b042f6865f40d01 100644
--- a/llvm/lib/Target/X86/X86FrameLowering.cpp
+++ b/llvm/lib/Target/X86/X86FrameLowering.cpp
@@ -68,8 +68,8 @@ bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
/// call frame pseudos can be simplified. Having a FP, as in the default
/// implementation, is not sufficient here since we can't always use it.
/// Use a more nuanced condition.
-bool
-X86FrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {
+bool X86FrameLowering::canSimplifyCallFramePseudos(
+ const MachineFunction &MF) const {
return hasReservedCallFrame(MF) ||
MF.getInfo<X86MachineFunctionInfo>()->hasPreallocatedCall() ||
(hasFP(MF) && !TRI->hasStackRealignment(MF)) ||
@@ -83,8 +83,8 @@ X86FrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {
// that were not simplified earlier.
// So, this is required for x86 functions that have push sequences even
// when there are no stack objects.
-bool
-X86FrameLowering::needsFrameIndexResolution(const MachineFunction &MF) const {
+bool X86FrameLowering::needsFrameIndexResolution(
+ const MachineFunction &MF) const {
return MF.getFrameInfo().hasStackObjects() ||
MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
}
@@ -194,8 +194,8 @@ flagsNeedToBePreservedBeforeTheTerminators(const MachineBasicBlock &MBB) {
/// stack pointer by a constant value.
void X86FrameLowering::emitSPUpdate(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI,
- const DebugLoc &DL,
- int64_t NumBytes, bool InEpilogue) const {
+ const DebugLoc &DL, int64_t NumBytes,
+ bool InEpilogue) const {
bool isSub = NumBytes < 0;
uint64_t Offset = isSub ? -NumBytes : NumBytes;
MachineInstr::MIFlag Flag =
@@ -279,13 +279,11 @@ void X86FrameLowering::emitSPUpdate(MachineBasicBlock &MBB,
if (ThisVal == SlotSize) {
// Use push / pop for slot sized adjustments as a size optimization. We
// need to find a dead register when using pop.
- unsigned Reg = isSub
- ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
- : TRI->findDeadCallerSavedReg(MBB, MBBI);
+ unsigned Reg = isSub ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
+ : TRI->findDeadCallerSavedReg(MBB, MBBI);
if (Reg) {
- unsigned Opc = isSub
- ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
- : (Is64Bit ? X86::POP64r : X86::POP32r);
+ unsigned Opc = isSub ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
+ : (Is64Bit ? X86::POP64r : X86::POP32r);
BuildMI(MBB, MBBI, DL, TII.get(Opc))
.addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub))
.setMIFlag(Flag);
@@ -922,24 +920,16 @@ void X86FrameLowering::emitStackProbeInlineWindowsCoreCLR64(
// registers. For the prolog expansion we use RAX, RCX and RDX.
MachineRegisterInfo &MRI = MF.getRegInfo();
const TargetRegisterClass *RegClass = &X86::GR64RegClass;
- const Register SizeReg = InProlog ? X86::RAX
- : MRI.createVirtualRegister(RegClass),
- ZeroReg = InProlog ? X86::RCX
- : MRI.createVirtualRegister(RegClass),
- CopyReg = InProlog ? X86::RDX
- : MRI.createVirtualRegister(RegClass),
- TestReg = InProlog ? X86::RDX
- : MRI.createVirtualRegister(RegClass),
- FinalReg = InProlog ? X86::RDX
- : MRI.createVirtualRegister(RegClass),
- RoundedReg = InProlog ? X86::RDX
- : MRI.createVirtualRegister(RegClass),
- LimitReg = InProlog ? X86::RCX
- : MRI.createVirtualRegister(RegClass),
- JoinReg = InProlog ? X86::RCX
- : MRI.createVirtualRegister(RegClass),
- ProbeReg = InProlog ? X86::RCX
- : MRI.createVirtualRegister(RegClass);
+ const Register
+ SizeReg = InProlog ? X86::RAX : MRI.createVirtualRegister(RegClass),
+ ZeroReg = InProlog ? X86::RCX : MRI.createVirtualRegister(RegClass),
+ CopyReg = InProlog ? X86::RDX : MRI.createVirtualRegister(RegClass),
+ TestReg = InProlog ? X86::RDX : MRI.createVirtualRegister(RegClass),
+ FinalReg = InProlog ? X86::RDX : MRI.createVirtualRegister(RegClass),
+ RoundedReg = InProlog ? X86::RDX : MRI.createVirtualRegister(RegClass),
+ LimitReg = InProlog ? X86::RCX : MRI.createVirtualRegister(RegClass),
+ JoinReg = InProlog ? X86::RCX : MRI.createVirtualRegister(RegClass),
+ ProbeReg = InProlog ? X86::RCX : MRI.createVirtualRegister(RegClass);
// SP-relative offsets where we can save RCX and RDX.
int64_t RCXShadowSlot = 0;
@@ -1011,7 +1001,9 @@ void X86FrameLowering::emitStackProbeInlineWindowsCoreCLR64(
.addReg(X86::GS);
BuildMI(&MBB, DL, TII.get(X86::CMP64rr)).addReg(FinalReg).addReg(LimitReg);
// Jump if the desired stack pointer is at or above the stack limit.
- BuildMI(&MBB, DL, TII.get(X86::JCC_1)).addMBB(ContinueMBB).addImm(X86::COND_AE);
+ BuildMI(&MBB, DL, TII.get(X86::JCC_1))
+ .addMBB(ContinueMBB)
+ .addImm(X86::COND_AE);
// Add code to roundMBB to round the final stack pointer to a page boundary.
RoundMBB->addLiveIn(FinalReg);
@@ -1048,7 +1040,9 @@ void X86FrameLowering::emitStackProbeInlineWindowsCoreCLR64(
BuildMI(LoopMBB, DL, TII.get(X86::CMP64rr))
.addReg(RoundedReg)
.addReg(ProbeReg);
- BuildMI(LoopMBB, DL, TII.get(X86::JCC_1)).addMBB(LoopMBB).addImm(X86::COND_NE);
+ BuildMI(LoopMBB, DL, TII.get(X86::JCC_1))
+ .addMBB(LoopMBB)
+ .addImm(X86::COND_NE);
MachineBasicBlock::iterator ContinueMBBI = ContinueMBB->getFirstNonPHI();
@@ -1132,7 +1126,7 @@ void X86FrameLowering::emitStackProbeCall(
CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addReg(X86::R11);
} else {
CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp))
- .addExternalSymbol(MF.createExternalSymbolName(Symbol));
+ .addExternalSymbol(MF.createExternalSymbolName(Symbol));
}
unsigned AX = Uses64BitFramePtr ? X86::RAX : X86::EAX;
@@ -1194,7 +1188,8 @@ static unsigned calculateSetFPREG(uint64_t SPAdjust) {
// info, we need to know the ABI stack alignment as well in case we
// have a call out. Otherwise just make sure we have some alignment - we'll
// go with the minimum SlotSize.
-uint64_t X86FrameLowering::calculateMaxStackAlign(const MachineFunction &MF) const {
+uint64_t
+X86FrameLowering::calculateMaxStackAlign(const MachineFunction &MF) const {
const MachineFrameInfo &MFI = MF.getFrameInfo();
Align MaxAlign = MFI.getMaxAlign(); // Desired stack alignment.
Align StackAlign = getStackAlign();
@@ -1285,8 +1280,7 @@ void X86FrameLowering::BuildStackAlignAND(MachineBasicBlock &MBB,
// Loop entry block
{
- const unsigned SUBOpc =
- getSUBriOpcode(Uses64BitFramePtr);
+ const unsigned SUBOpc = getSUBriOpcode(Uses64BitFramePtr);
BuildMI(headMBB, DL, TII.get(SUBOpc), StackPtr)
.addReg(StackPtr)
.addImm(StackProbeSize)
@@ -1316,8 +1310,7 @@ void X86FrameLowering::BuildStackAlignAND(MachineBasicBlock &MBB,
.addImm(0)
.setMIFlag(MachineInstr::FrameSetup);
- const unsigned SUBOpc =
- getSUBriOpcode(Uses64BitFramePtr);
+ const unsigned SUBOpc = getSUBriOpcode(Uses64BitFramePtr);
BuildMI(bodyMBB, DL, TII.get(SUBOpc), StackPtr)
.addReg(StackPtr)
.addImm(StackProbeSize)
@@ -1368,7 +1361,7 @@ void X86FrameLowering::BuildStackAlignAND(MachineBasicBlock &MBB,
}
}
-bool X86FrameLowering::has128ByteRedZone(const MachineFunction& MF) const {
+bool X86FrameLowering::has128ByteRedZone(const MachineFunction &MF) const {
// x86-64 (non Win64) has a 128 byte red zone which is guaranteed not to be
// clobbered by any interrupt handler.
assert(&STI == &MF.getSubtarget<X86Subtarget>() &&
@@ -1484,7 +1477,7 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF,
MachineModuleInfo &MMI = MF.getMMI();
X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
uint64_t MaxAlign = calculateMaxStackAlign(MF); // Desired stack alignment.
- uint64_t StackSize = MFI.getStackSize(); // Number of bytes to allocate.
+ uint64_t StackSize = MFI.getStackSize(); // Number of bytes to allocate.
bool IsFunclet = MBB.isEHFuncletEntry();
EHPersonality Personality = EHPersonality::Unknown;
if (Fn.hasPersonalityFn())
@@ -1502,8 +1495,8 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF,
bool NeedsDwarfCFI = needsDwarfCFI(MF);
Register FramePtr = TRI->getFrameRegister(MF);
const Register MachineFramePtr =
- STI.isTarget64BitILP32()
- ? Register(getX86SubSuperRegister(FramePtr, 64)) : FramePtr;
+ STI.isTarget64BitILP32() ? Register(getX86SubSuperRegister(FramePtr, 64))
+ : FramePtr;
Register BasePtr = TRI->getBaseRegister();
bool HasWinCFI = false;
@@ -1538,7 +1531,7 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF,
}
BuildStackAlignAND(MBB, MBBI, DL, StackPtr, MaxAlign);
int64_t Offset = -(int64_t)SlotSize;
- BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64rmm: X86::PUSH32rmm))
+ BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64rmm : X86::PUSH32rmm))
.addReg(ArgBaseReg)
.addImm(1)
.addReg(X86::NoRegister)
@@ -1550,7 +1543,7 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF,
// Space reserved for stack-based arguments when making a (ABI-guaranteed)
// tail call.
unsigned TailCallArgReserveSize = -X86FI->getTCReturnAddrDelta();
- if (TailCallArgReserveSize && IsWin64Prologue)
+ if (TailCallArgReserveSize && IsWin64Prologue)
report_fatal_error("Can't handle guaranteed tail call under win64 yet");
const bool EmitStackProbeCall =
@@ -1622,7 +1615,8 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF,
!MF.shouldSplitStack()) { // Regular stack
uint64_t MinSize =
X86FI->getCalleeSavedFrameSize() - X86FI->getTCReturnAddrDelta();
- if (HasFP) MinSize += SlotSize;
+ if (HasFP)
+ MinSize += SlotSize;
X86FI->setUsesRedZone(MinSize > 0 || StackSize > 0);
StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
MFI.setStackSize(StackSize);
@@ -1677,8 +1671,8 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF,
// Calculate required stack adjustment.
uint64_t FrameSize = StackSize - SlotSize;
- NumBytes = FrameSize -
- (X86FI->getCalleeSavedFrameSize() + TailCallArgReserveSize);
+ NumBytes =
+ FrameSize - (X86FI->getCalleeSavedFrameSize() + TailCallArgReserveSize);
// Callee-saved registers are pushed on stack before the stack is realigned.
if (TRI->hasStackRealignment(MF) && !IsWin64Prologue)
@@ -1686,8 +1680,8 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF,
// Save EBP/RBP into the appropriate stack slot.
BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
- .addReg(MachineFramePtr, RegState::Kill)
- .setMIFlag(MachineInstr::FrameSetup);
+ .addReg(MachineFramePtr, RegState::Kill)
+ .setMIFlag(MachineInstr::FrameSetup);
if (NeedsDwarfCFI && !ArgBaseReg.isValid()) {
// Mark the place where EBP/RBP was saved.
@@ -1802,8 +1796,8 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF,
}
} else {
assert(!IsFunclet && "funclets without FPs not yet implemented");
- NumBytes = StackSize -
- (X86FI->getCalleeSavedFrameSize() + TailCallArgReserveSize);
+ NumBytes =
+ StackSize - (X86FI->getCalleeSavedFrameSize() + TailCallArgReserveSize);
}
// Update the offset adjustment, which is mainly used by codeview to translate
@@ -1825,8 +1819,7 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF,
bool PushedRegs = false;
int StackOffset = 2 * stackGrowth;
- while (MBBI != MBB.end() &&
- MBBI->getFlag(MachineInstr::FrameSetup) &&
+ while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup) &&
(MBBI->getOpcode() == X86::PUSH32r ||
MBBI->getOpcode() == X86::PUSH64r)) {
PushedRegs = true;
@@ -1896,13 +1889,13 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF,
if (Is64Bit) {
// Save RAX
BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r))
- .addReg(X86::RAX, RegState::Kill)
- .setMIFlag(MachineInstr::FrameSetup);
+ .addReg(X86::RAX, RegState::Kill)
+ .setMIFlag(MachineInstr::FrameSetup);
} else {
// Save EAX
BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
- .addReg(X86::EAX, RegState::Kill)
- .setMIFlag(MachineInstr::FrameSetup);
+ .addReg(X86::EAX, RegState::Kill)
+ .setMIFlag(MachineInstr::FrameSetup);
}
}
@@ -2085,16 +2078,16 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF,
// Update the base pointer with the current stack pointer.
unsigned Opc = Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr;
BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
- .addReg(SPOrEstablisher)
- .setMIFlag(MachineInstr::FrameSetup);
+ .addReg(SPOrEstablisher)
+ .setMIFlag(MachineInstr::FrameSetup);
if (X86FI->getRestoreBasePointer()) {
// Stash value of base pointer. Saving RSP instead of EBP shortens
// dependence chain. Used by SjLj EH.
unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
- addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)),
- FramePtr, true, X86FI->getRestoreBasePointerOffset())
- .addReg(SPOrEstablisher)
- .setMIFlag(MachineInstr::FrameSetup);
+ addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)), FramePtr, true,
+ X86FI->getRestoreBasePointerOffset())
+ .addReg(SPOrEstablisher)
+ .setMIFlag(MachineInstr::FrameSetup);
}
if (X86FI->getHasSEHFramePtrSave() && !IsFunclet) {
@@ -2207,9 +2200,9 @@ X86FrameLowering::getWinEHFuncletFrameSize(const MachineFunction &MF) const {
// This is the size of the pushed CSRs.
unsigned CSSize = X86FI->getCalleeSavedFrameSize();
// This is the size of callee saved XMMs.
- const auto& WinEHXMMSlotInfo = X86FI->getWinEHXMMSlotInfo();
- unsigned XMMSize = WinEHXMMSlotInfo.size() *
- TRI->getSpillSize(X86::VR128RegClass);
+ const auto &WinEHXMMSlotInfo = X86FI->getWinEHXMMSlotInfo();
+ unsigned XMMSize =
+ WinEHXMMSlotInfo.size() * TRI->getSpillSize(X86::VR128RegClass);
// This is the amount of stack a funclet needs to allocate.
unsigned UsedSize;
EHPersonality Personality =
@@ -2233,10 +2226,9 @@ X86FrameLowering::getWinEHFuncletFrameSize(const MachineFunction &MF) const {
}
static bool isTailCallOpcode(unsigned Opc) {
- return Opc == X86::TCRETURNri || Opc == X86::TCRETURNdi ||
- Opc == X86::TCRETURNmi ||
- Opc == X86::TCRETURNri64 || Opc == X86::TCRETURNdi64 ||
- Opc == X86::TCRETURNmi64;
+ return Opc == X86::TCRETURNri || Opc == X86::TCRETURNdi ||
+ Opc == X86::TCRETURNmi || Opc == X86::TCRETURNri64 ||
+ Opc == X86::TCRETURNdi64 || Opc == X86::TCRETURNmi64;
}
void X86FrameLowering::emitEpilogue(MachineFunction &MF,
@@ -2322,7 +2314,7 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF,
if (X86FI->hasSwiftAsyncContext()) {
// Discard the context.
int Offset = 16 + mergeSPUpdates(MBB, MBBI, true);
- emitSPUpdate(MBB, MBBI, DL, Offset, /*InEpilogue*/true);
+ emitSPUpdate(MBB, MBBI, DL, Offset, /*InEpilogue*/ true);
}
// Pop EBP.
BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::POP64r : X86::POP32r),
@@ -2332,8 +2324,7 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF,
// We need to reset FP to its untagged state on return. Bit 60 is currently
// used to show the presence of an extended frame.
if (X86FI->hasSwiftAsyncContext()) {
- BuildMI(MBB, MBBI, DL, TII.get(X86::BTR64ri8),
- MachineFramePtr)
+ BuildMI(MBB, MBBI, DL, TII.get(X86::BTR64ri8), MachineFramePtr)
.addUse(MachineFramePtr)
.addImm(60)
.setMIFlag(MachineInstr::FrameDestroy);
@@ -2421,13 +2412,12 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF,
// effects of the prologue can safely be undone.
if (LEAAmount != 0) {
unsigned Opc = getLEArOpcode(Uses64BitFramePtr);
- addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
- FramePtr, false, LEAAmount);
+ addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr), FramePtr,
+ false, LEAAmount);
--MBBI;
} else {
unsigned Opc = (Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr);
- BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
- .addReg(FramePtr);
+ BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr).addReg(FramePtr);
--MBBI;
}
} else if (NumBytes) {
@@ -2533,7 +2523,8 @@ StackOffset X86FrameLowering::getFrameIndexReference(const MachineFunction &MF,
// Calculate required stack adjustment.
uint64_t FrameSize = StackSize - SlotSize;
- // If required, include space for extra hidden slot for stashing base pointer.
+ // If required, include space for extra hidden slot for stashing base
+ // pointer.
if (X86FI->getRestoreBasePointer())
FrameSize += SlotSize;
uint64_t NumBytes = FrameSize - CSSize;
@@ -2578,7 +2569,7 @@ int X86FrameLowering::getWin64EHFrameIndexRef(const MachineFunction &MF, int FI,
Register &FrameReg) const {
const MachineFrameInfo &MFI = MF.getFrameInfo();
const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
- const auto& WinEHXMMSlotInfo = X86FI->getWinEHXMMSlotInfo();
+ const auto &WinEHXMMSlotInfo = X86FI->getWinEHXMMSlotInfo();
const auto it = WinEHXMMSlotInfo.find(FI);
if (it == WinEHXMMSlotInfo.end())
@@ -2706,7 +2697,7 @@ bool X86FrameLowering::assignCalleeSavedSpillSlots(
// }
// [EBP]
MFI.CreateFixedObject(-TailCallReturnAddrDelta,
- TailCallReturnAddrDelta - SlotSize, true);
+ TailCallReturnAddrDelta - SlotSize, true);
}
// Spill the BasePtr if it's used.
@@ -2737,7 +2728,7 @@ bool X86FrameLowering::assignCalleeSavedSpillSlots(
// about avoiding it later.
Register FPReg = TRI->getFrameRegister(MF);
for (unsigned i = 0; i < CSI.size(); ++i) {
- if (TRI->regsOverlap(CSI[i].getReg(),FPReg)) {
+ if (TRI->regsOverlap(CSI[i].getReg(), FPReg)) {
CSI.erase(CSI.begin() + i);
break;
}
@@ -2846,8 +2837,9 @@ bool X86FrameLowering::spillCalleeSavedRegisters(
// passed in callee saved registers.
// Omitting the kill flags is conservatively correct even if the live-in
// is not used after all.
- BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, getKillRegState(CanKill))
- .setMIFlag(MachineInstr::FrameSetup);
+ BuildMI(MBB, MI, DL, TII.get(Opc))
+ .addReg(Reg, getKillRegState(CanKill))
+ .setMIFlag(MachineInstr::FrameSetup);
}
const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
@@ -2942,8 +2934,7 @@ bool X86FrameLowering::restoreCalleeSavedRegisters(
// Reload XMMs from stack frame.
for (const CalleeSavedInfo &I : CSI) {
Register Reg = I.getReg();
- if (X86::GR64RegClass.contains(Reg) ||
- X86::GR32RegClass.contains(Reg))
+ if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
continue;
// If this is k-register make sure we lookup via the largest legal type.
@@ -2970,8 +2961,7 @@ bool X86FrameLowering::restoreCalleeSavedRegisters(
unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
for (const CalleeSavedInfo &I : CSI) {
Register Reg = I.getReg();
- if (!X86::GR64RegClass.contains(Reg) &&
- !X86::GR32RegClass.contains(Reg))
+ if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
continue;
BuildMI(MBB, MI, DL, TII.get(Opc), Reg)
@@ -2986,7 +2976,7 @@ void X86FrameLowering::determineCalleeSaves(MachineFunction &MF,
TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
// Spill the BasePtr if it's used.
- if (TRI->hasBasePointer(MF)){
+ if (TRI->hasBasePointer(MF)) {
Register BasePtr = TRI->getBaseRegister();
if (STI.isTarget64BitILP32())
BasePtr = getX86SubSuperRegister(BasePtr, 64);
@@ -2994,11 +2984,10 @@ void X86FrameLowering::determineCalleeSaves(MachineFunction &MF,
}
}
-static bool
-HasNestArgument(const MachineFunction *MF) {
+static bool HasNestArgument(const MachineFunction *MF) {
const Function &F = MF->getFunction();
- for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
- I != E; I++) {
+ for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
+ I++) {
if (I->hasNestAttr() && !I->use_empty())
return true;
}
@@ -3009,8 +2998,8 @@ HasNestArgument(const MachineFunction *MF) {
/// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
/// and the properties of the function either one or two registers will be
/// needed. Set primary to true for the first register, false for the second.
-static unsigned
-GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary) {
+static unsigned GetScratchRegister(bool Is64Bit, bool IsLP64,
+ const MachineFunction &MF, bool Primary) {
CallingConv::ID CallingConvention = MF.getFunction().getCallingConv();
// Erlang stuff.
@@ -3111,7 +3100,7 @@ void X86FrameLowering::adjustForSegmentedStacks(
TlsOffset = IsLP64 ? 0x70 : 0x40;
} else if (STI.isTargetDarwin()) {
TlsReg = X86::GS;
- TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
+ TlsOffset = 0x60 + 90 * 8; // See pthread_machdep.h. Steal TLS slot 90.
} else if (STI.isTargetWin64()) {
TlsReg = X86::GS;
TlsOffset = 0x28; // pvArbitrary, reserved for application use
@@ -3128,18 +3117,28 @@ void X86FrameLowering::adjustForSegmentedStacks(
if (CompareStackPointer)
ScratchReg = IsLP64 ? X86::RSP : X86::ESP;
else
- BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r), ScratchReg).addReg(X86::RSP)
- .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
-
- BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::CMP64rm : X86::CMP32rm)).addReg(ScratchReg)
- .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
+ BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r),
+ ScratchReg)
+ .addReg(X86::RSP)
+ .addImm(1)
+ .addReg(0)
+ .addImm(-StackSize)
+ .addReg(0);
+
+ BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::CMP64rm : X86::CMP32rm))
+ .addReg(ScratchReg)
+ .addReg(0)
+ .addImm(1)
+ .addReg(0)
+ .addImm(TlsOffset)
+ .addReg(TlsReg);
} else {
if (STI.isTargetLinux()) {
TlsReg = X86::GS;
TlsOffset = 0x30;
} else if (STI.isTargetDarwin()) {
TlsReg = X86::GS;
- TlsOffset = 0x48 + 90*4;
+ TlsOffset = 0x48 + 90 * 4;
} else if (STI.isTargetWin32()) {
TlsReg = X86::FS;
TlsOffset = 0x14; // pvArbitrary, reserved for application use
@@ -3155,13 +3154,22 @@ void X86FrameLowering::adjustForSegmentedStacks(
if (CompareStackPointer)
ScratchReg = X86::ESP;
else
- BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
- .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
+ BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg)
+ .addReg(X86::ESP)
+ .addImm(1)
+ .addReg(0)
+ .addImm(-StackSize)
+ .addReg(0);
if (STI.isTargetLinux() || STI.isTargetWin32() || STI.isTargetWin64() ||
STI.isTargetDragonFly()) {
- BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
- .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
+ BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
+ .addReg(ScratchReg)
+ .addReg(0)
+ .addImm(0)
+ .addReg(0)
+ .addImm(TlsOffset)
+ .addReg(TlsReg);
} else if (STI.isTargetDarwin()) {
// TlsOffset doesn't fit into a mod r/m byte so we need an extra register.
@@ -3186,15 +3194,17 @@ void X86FrameLowering::adjustForSegmentedStacks(
if (SaveScratch2)
BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
- .addReg(ScratchReg2, RegState::Kill);
+ .addReg(ScratchReg2, RegState::Kill);
BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
- .addImm(TlsOffset);
+ .addImm(TlsOffset);
BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
- .addReg(ScratchReg)
- .addReg(ScratchReg2).addImm(1).addReg(0)
- .addImm(0)
- .addReg(TlsReg);
+ .addReg(ScratchReg)
+ .addReg(ScratchReg2)
+ .addImm(1)
+ .addReg(0)
+ .addImm(0)
+ .addReg(TlsReg);
if (SaveScratch2)
BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
@@ -3203,7 +3213,9 @@ void X86FrameLowering::adjustForSegmentedStacks(
// This jump is taken if SP >= (Stacklet Limit + Stack Space required).
// It jumps to normal execution of the function body.
- BuildMI(checkMBB, DL, TII.get(X86::JCC_1)).addMBB(&PrologueMBB).addImm(X86::COND_A);
+ BuildMI(checkMBB, DL, TII.get(X86::JCC_1))
+ .addMBB(&PrologueMBB)
+ .addImm(X86::COND_A);
// On 32 bit we first push the arguments size and then the frame size. On 64
// bit, we pass the stack frame size in r10 and the argument size in r11.
@@ -3227,9 +3239,8 @@ void X86FrameLowering::adjustForSegmentedStacks(
.addImm(X86FI->getArgumentStackSize());
} else {
BuildMI(allocMBB, DL, TII.get(X86::PUSH32i))
- .addImm(X86FI->getArgumentStackSize());
- BuildMI(allocMBB, DL, TII.get(X86::PUSH32i))
- .addImm(StackSize);
+ .addImm(X86FI->getArgumentStackSize());
+ BuildMI(allocMBB, DL, TII.get(X86::PUSH32i)).addImm(StackSize);
}
// __morestack is in libgcc
@@ -3261,10 +3272,10 @@ void X86FrameLowering::adjustForSegmentedStacks(
} else {
if (Is64Bit)
BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
- .addExternalSymbol("__morestack");
+ .addExternalSymbol("__morestack");
else
BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
- .addExternalSymbol("__morestack");
+ .addExternalSymbol("__morestack");
}
if (IsNested)
@@ -3286,22 +3297,24 @@ void X86FrameLowering::adjustForSegmentedStacks(
/// HiPE provides Erlang Runtime System-internal parameters, such as PCB offsets
/// to fields it needs, through a named metadata node "hipe.literals" containing
/// name-value pairs.
-static unsigned getHiPELiteral(
- NamedMDNode *HiPELiteralsMD, const StringRef LiteralName) {
+static unsigned getHiPELiteral(NamedMDNode *HiPELiteralsMD,
+ const StringRef LiteralName) {
for (int i = 0, e = HiPELiteralsMD->getNumOperands(); i != e; ++i) {
MDNode *Node = HiPELiteralsMD->getOperand(i);
- if (Node->getNumOperands() != 2) continue;
+ if (Node->getNumOperands() != 2)
+ continue;
MDString *NodeName = dyn_cast<MDString>(Node->getOperand(0));
ValueAsMetadata *NodeVal = dyn_cast<ValueAsMetadata>(Node->getOperand(1));
- if (!NodeName || !NodeVal) continue;
+ if (!NodeName || !NodeVal)
+ continue;
ConstantInt *ValConst = dyn_cast_or_null<ConstantInt>(NodeVal->getValue());
if (ValConst && NodeName->getString() == LiteralName) {
return ValConst->getZExtValue();
}
}
- report_fatal_error("HiPE literal " + LiteralName
- + " required but not provided");
+ report_fatal_error("HiPE literal " + LiteralName +
+ " required but not provided");
}
// Return true if there are no non-ehpad successors to MBB and there are no
@@ -3341,19 +3354,19 @@ void X86FrameLowering::adjustForHiPEPrologue(
assert(&(*MF.begin()) == &PrologueMBB && "Shrink-wrapping not supported yet");
// HiPE-specific values
- NamedMDNode *HiPELiteralsMD = MF.getMMI().getModule()
- ->getNamedMetadata("hipe.literals");
+ NamedMDNode *HiPELiteralsMD =
+ MF.getMMI().getModule()->getNamedMetadata("hipe.literals");
if (!HiPELiteralsMD)
report_fatal_error(
"Can't generate HiPE prologue without runtime parameters");
- const unsigned HipeLeafWords
- = getHiPELiteral(HiPELiteralsMD,
- Is64Bit ? "AMD64_LEAF_WORDS" : "X86_LEAF_WORDS");
+ const unsigned HipeLeafWords = getHiPELiteral(
+ HiPELiteralsMD, Is64Bit ? "AMD64_LEAF_WORDS" : "X86_LEAF_WORDS");
const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
const unsigned Guaranteed = HipeLeafWords * SlotSize;
- unsigned CallerStkArity = MF.getFunction().arg_size() > CCRegisteredArgs ?
- MF.getFunction().arg_size() - CCRegisteredArgs : 0;
- unsigned MaxStack = MFI.getStackSize() + CallerStkArity*SlotSize + SlotSize;
+ unsigned CallerStkArity = MF.getFunction().arg_size() > CCRegisteredArgs
+ ? MF.getFunction().arg_size() - CCRegisteredArgs
+ : 0;
+ unsigned MaxStack = MFI.getStackSize() + CallerStkArity * SlotSize + SlotSize;
assert(STI.isTargetLinux() &&
"HiPE prologue is only supported on Linux operating systems.");
@@ -3393,11 +3406,13 @@ void X86FrameLowering::adjustForHiPEPrologue(
F->getName().find_first_of("._") == StringRef::npos)
continue;
- unsigned CalleeStkArity =
- F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
+ unsigned CalleeStkArity = F->arg_size() > CCRegisteredArgs
+ ? F->arg_size() - CCRegisteredArgs
+ : 0;
if (HipeLeafWords - 1 > CalleeStkArity)
- MoreStackForCalls = std::max(MoreStackForCalls,
- (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
+ MoreStackForCalls =
+ std::max(MoreStackForCalls,
+ (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
}
}
MaxStack += MoreStackForCalls;
@@ -3422,13 +3437,13 @@ void X86FrameLowering::adjustForHiPEPrologue(
SPLimitOffset = getHiPELiteral(HiPELiteralsMD, "P_NSP_LIMIT");
if (Is64Bit) {
SPReg = X86::RSP;
- PReg = X86::RBP;
+ PReg = X86::RBP;
LEAop = X86::LEA64r;
CMPop = X86::CMP64rm;
CALLop = X86::CALL64pcrel32;
} else {
SPReg = X86::ESP;
- PReg = X86::EBP;
+ PReg = X86::EBP;
LEAop = X86::LEA32r;
CMPop = X86::CMP32rm;
CALLop = X86::CALLpcrel32;
@@ -3439,21 +3454,24 @@ void X86FrameLowering::adjustForHiPEPrologue(
"HiPE prologue scratch register is live-in");
// Create new MBB for StackCheck:
- addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
- SPReg, false, -MaxStack);
+ addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg), SPReg,
+ false, -MaxStack);
// SPLimitOffset is in a fixed heap location (pointed by BP).
- addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
- .addReg(ScratchReg), PReg, false, SPLimitOffset);
- BuildMI(stackCheckMBB, DL, TII.get(X86::JCC_1)).addMBB(&PrologueMBB).addImm(X86::COND_AE);
+ addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop)).addReg(ScratchReg),
+ PReg, false, SPLimitOffset);
+ BuildMI(stackCheckMBB, DL, TII.get(X86::JCC_1))
+ .addMBB(&PrologueMBB)
+ .addImm(X86::COND_AE);
// Create new MBB for IncStack:
- BuildMI(incStackMBB, DL, TII.get(CALLop)).
- addExternalSymbol("inc_stack_0");
- addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
- SPReg, false, -MaxStack);
- addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
- .addReg(ScratchReg), PReg, false, SPLimitOffset);
- BuildMI(incStackMBB, DL, TII.get(X86::JCC_1)).addMBB(incStackMBB).addImm(X86::COND_LE);
+ BuildMI(incStackMBB, DL, TII.get(CALLop)).addExternalSymbol("inc_stack_0");
+ addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg), SPReg,
+ false, -MaxStack);
+ addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop)).addReg(ScratchReg),
+ PReg, false, SPLimitOffset);
+ BuildMI(incStackMBB, DL, TII.get(X86::JCC_1))
+ .addMBB(incStackMBB)
+ .addImm(X86::COND_LE);
stackCheckMBB->addSuccessor(&PrologueMBB, {99, 100});
stackCheckMBB->addSuccessor(incStackMBB, {1, 100});
@@ -3533,15 +3551,15 @@ bool X86FrameLowering::adjustStackWithPops(MachineBasicBlock &MBB,
Regs[FoundRegs++] = Regs[0];
for (int i = 0; i < NumPops; ++i)
- BuildMI(MBB, MBBI, DL,
- TII.get(STI.is64Bit() ? X86::POP64r : X86::POP32r), Regs[i]);
+ BuildMI(MBB, MBBI, DL, TII.get(STI.is64Bit() ? X86::POP64r : X86::POP32r),
+ Regs[i]);
return true;
}
-MachineBasicBlock::iterator X86FrameLowering::
-eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I) const {
+MachineBasicBlock::iterator X86FrameLowering::eliminateCallFramePseudoInstr(
+ MachineFunction &MF, MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator I) const {
bool reserveCallFrame = hasReservedCallFrame(MF);
unsigned Opcode = I->getOpcode();
bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
@@ -3629,9 +3647,9 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
// TODO: When not using precise CFA, we also need to adjust for the
// InternalAmt here.
if (CfaAdjustment) {
- BuildCFI(MBB, InsertPos, DL,
- MCCFIInstruction::createAdjustCfaOffset(nullptr,
- CfaAdjustment));
+ BuildCFI(
+ MBB, InsertPos, DL,
+ MCCFIInstruction::createAdjustCfaOffset(nullptr, CfaAdjustment));
}
}
@@ -3800,11 +3818,11 @@ X86FrameLowering::getDwarfFrameBase(const MachineFunction &MF) const {
namespace {
// Struct used by orderFrameObjects to help sort the stack objects.
struct X86FrameSortingObject {
- bool IsValid = false; // true if we care about this Object.
- unsigned ObjectIndex = 0; // Index of Object into MFI list.
- unsigned ObjectSize = 0; // Size of Object in bytes.
+ bool IsValid = false; // true if we care about this Object.
+ unsigned ObjectIndex = 0; // Index of Object into MFI list.
+ unsigned ObjectSize = 0; // Size of Object in bytes.
Align ObjectAlignment = Align(1); // Alignment of Object in bytes.
- unsigned ObjectNumUses = 0; // Object static number of uses.
+ unsigned ObjectNumUses = 0; // Object static number of uses.
};
// The comparison function we use for std::sort to order our local
@@ -3844,9 +3862,9 @@ struct X86FrameSortingComparator {
// the division and, with it, the need for any floating point
// arithmetic.
DensityAScaled = static_cast<uint64_t>(A.ObjectNumUses) *
- static_cast<uint64_t>(B.ObjectSize);
+ static_cast<uint64_t>(B.ObjectSize);
DensityBScaled = static_cast<uint64_t>(B.ObjectNumUses) *
- static_cast<uint64_t>(A.ObjectSize);
+ static_cast<uint64_t>(A.ObjectSize);
// If the two densities are equal, prioritize highest alignment
// objects. This allows for similar alignment objects
@@ -3939,8 +3957,8 @@ void X86FrameLowering::orderFrameObjects(
std::reverse(ObjectsToAllocate.begin(), ObjectsToAllocate.end());
}
-
-unsigned X86FrameLowering::getWinEHParentFrameOffset(const MachineFunction &MF) const {
+unsigned
+X86FrameLowering::getWinEHParentFrameOffset(const MachineFunction &MF) const {
// RDX, the parent frame pointer, is homed into 16(%rsp) in the prologue.
unsigned Offset = 16;
// RBP is immediately pushed.
More information about the llvm-commits
mailing list