[llvm] [SelectionDAG] Add space-optimized forms of OPC_EmitConvertToTarget (PR #73286)
Wang Pengcheng via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 23 22:10:49 PST 2023
https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/73286
These new opcodes implicitly indicate the RecNo.
Overall this reduces the llc binary size with all in-tree targets by
about 13K.
>From 1b027dcbf350df9943650c28f24dbb92c1cbaea3 Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Fri, 24 Nov 2023 14:09:40 +0800
Subject: [PATCH] [SelectionDAG] Add space-optimized forms of
OPC_EmitConvertToTarget
These new opcodes implicitly indicate the RecNo.
Overall this reduces the llc binary size with all in-tree targets by
about 13K.
---
llvm/include/llvm/CodeGen/SelectionDAGISel.h | 8 ++++++++
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 14 ++++++++++++--
llvm/utils/TableGen/DAGISelMatcherEmitter.cpp | 11 ++++++++---
3 files changed, 28 insertions(+), 5 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index e6513eb6abc8749..aa23d68a7570b31 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -187,6 +187,14 @@ class SelectionDAGISel : public MachineFunctionPass {
OPC_EmitRegister,
OPC_EmitRegister2,
OPC_EmitConvertToTarget,
+ OPC_EmitConvertToTarget0,
+ OPC_EmitConvertToTarget1,
+ OPC_EmitConvertToTarget2,
+ OPC_EmitConvertToTarget3,
+ OPC_EmitConvertToTarget4,
+ OPC_EmitConvertToTarget5,
+ OPC_EmitConvertToTarget6,
+ OPC_EmitConvertToTarget7,
OPC_EmitMergeInputChains,
OPC_EmitMergeInputChains1_0,
OPC_EmitMergeInputChains1_1,
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 7d9bebdca127224..6f1f0bb5947c997 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -3486,9 +3486,19 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
continue;
}
- case OPC_EmitConvertToTarget: {
+ case OPC_EmitConvertToTarget:
+ case OPC_EmitConvertToTarget0:
+ case OPC_EmitConvertToTarget1:
+ case OPC_EmitConvertToTarget2:
+ case OPC_EmitConvertToTarget3:
+ case OPC_EmitConvertToTarget4:
+ case OPC_EmitConvertToTarget5:
+ case OPC_EmitConvertToTarget6:
+ case OPC_EmitConvertToTarget7: {
// Convert from IMM/FPIMM to target version.
- unsigned RecNo = MatcherTable[MatcherIndex++];
+ unsigned RecNo = Opcode == OPC_EmitConvertToTarget
+ ? MatcherTable[MatcherIndex++]
+ : Opcode - OPC_EmitConvertToTarget0;
assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget");
SDValue Imm = RecordedNodes[RecNo].first;
diff --git a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
index 4a11991036efc11..4a39f07c00e9049 100644
--- a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
@@ -707,10 +707,15 @@ EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx,
}
}
- case Matcher::EmitConvertToTarget:
- OS << "OPC_EmitConvertToTarget, "
- << cast<EmitConvertToTargetMatcher>(N)->getSlot() << ",\n";
+ case Matcher::EmitConvertToTarget: {
+ unsigned Slot = cast<EmitConvertToTargetMatcher>(N)->getSlot();
+ if (Slot < 8) {
+ OS << "OPC_EmitConvertToTarget" << Slot << ",\n";
+ return 1;
+ }
+ OS << "OPC_EmitConvertToTarget, " << Slot << ",\n";
return 2;
+ }
case Matcher::EmitMergeInputChains: {
const EmitMergeInputChainsMatcher *MN =
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