[llvm] be0307d - [SelectionDAG] Format BuiltinOpcodes

via llvm-commits llvm-commits at lists.llvm.org
Thu Nov 23 20:19:38 PST 2023


Author: wangpc
Date: 2023-11-24T12:18:46+08:00
New Revision: be0307d5769f87a2e64b7e9e78a78bcd3dcca800

URL: https://github.com/llvm/llvm-project/commit/be0307d5769f87a2e64b7e9e78a78bcd3dcca800
DIFF: https://github.com/llvm/llvm-project/commit/be0307d5769f87a2e64b7e9e78a78bcd3dcca800.diff

LOG: [SelectionDAG] Format BuiltinOpcodes

Added: 
    

Modified: 
    llvm/include/llvm/CodeGen/SelectionDAGISel.h

Removed: 
    


################################################################################
diff  --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index ffeb4959ba7d076..e6513eb6abc8749 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -124,17 +124,31 @@ class SelectionDAGISel : public MachineFunctionPass {
   enum BuiltinOpcodes {
     OPC_Scope,
     OPC_RecordNode,
-    OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3,
-    OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7,
+    OPC_RecordChild0,
+    OPC_RecordChild1,
+    OPC_RecordChild2,
+    OPC_RecordChild3,
+    OPC_RecordChild4,
+    OPC_RecordChild5,
+    OPC_RecordChild6,
+    OPC_RecordChild7,
     OPC_RecordMemRef,
     OPC_CaptureGlueInput,
     OPC_MoveChild,
-    OPC_MoveChild0, OPC_MoveChild1, OPC_MoveChild2, OPC_MoveChild3,
-    OPC_MoveChild4, OPC_MoveChild5, OPC_MoveChild6, OPC_MoveChild7,
+    OPC_MoveChild0,
+    OPC_MoveChild1,
+    OPC_MoveChild2,
+    OPC_MoveChild3,
+    OPC_MoveChild4,
+    OPC_MoveChild5,
+    OPC_MoveChild6,
+    OPC_MoveChild7,
     OPC_MoveParent,
     OPC_CheckSame,
-    OPC_CheckChild0Same, OPC_CheckChild1Same,
-    OPC_CheckChild2Same, OPC_CheckChild3Same,
+    OPC_CheckChild0Same,
+    OPC_CheckChild1Same,
+    OPC_CheckChild2Same,
+    OPC_CheckChild3Same,
     OPC_CheckPatternPredicate,
     OPC_CheckPatternPredicate2,
     OPC_CheckPredicate,
@@ -144,16 +158,26 @@ class SelectionDAGISel : public MachineFunctionPass {
     OPC_CheckType,
     OPC_CheckTypeRes,
     OPC_SwitchType,
-    OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type,
-    OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type,
-    OPC_CheckChild6Type, OPC_CheckChild7Type,
+    OPC_CheckChild0Type,
+    OPC_CheckChild1Type,
+    OPC_CheckChild2Type,
+    OPC_CheckChild3Type,
+    OPC_CheckChild4Type,
+    OPC_CheckChild5Type,
+    OPC_CheckChild6Type,
+    OPC_CheckChild7Type,
     OPC_CheckInteger,
-    OPC_CheckChild0Integer, OPC_CheckChild1Integer, OPC_CheckChild2Integer,
-    OPC_CheckChild3Integer, OPC_CheckChild4Integer,
-    OPC_CheckCondCode, OPC_CheckChild2CondCode,
+    OPC_CheckChild0Integer,
+    OPC_CheckChild1Integer,
+    OPC_CheckChild2Integer,
+    OPC_CheckChild3Integer,
+    OPC_CheckChild4Integer,
+    OPC_CheckCondCode,
+    OPC_CheckChild2CondCode,
     OPC_CheckValueType,
     OPC_CheckComplexPat,
-    OPC_CheckAndImm, OPC_CheckOrImm,
+    OPC_CheckAndImm,
+    OPC_CheckOrImm,
     OPC_CheckImmAllOnesV,
     OPC_CheckImmAllZerosV,
     OPC_CheckFoldableChainNode,
@@ -172,10 +196,14 @@ class SelectionDAGISel : public MachineFunctionPass {
     OPC_EmitNodeXForm,
     OPC_EmitNode,
     // Space-optimized forms that implicitly encode number of result VTs.
-    OPC_EmitNode0, OPC_EmitNode1, OPC_EmitNode2,
+    OPC_EmitNode0,
+    OPC_EmitNode1,
+    OPC_EmitNode2,
     OPC_MorphNodeTo,
     // Space-optimized forms that implicitly encode number of result VTs.
-    OPC_MorphNodeTo0, OPC_MorphNodeTo1, OPC_MorphNodeTo2,
+    OPC_MorphNodeTo0,
+    OPC_MorphNodeTo1,
+    OPC_MorphNodeTo2,
     OPC_CompleteMatch,
     // Contains offset in table for pattern being selected
     OPC_Coverage


        


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