[llvm] 39124f5 - [NFC][X86] Clang-format X86RecognizableInstr.cpp (#73278)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 23 19:45:27 PST 2023
Author: Shengchen Kan
Date: 2023-11-24T11:45:23+08:00
New Revision: 39124f525accda4002fd0a91dfe9c1d697709ad0
URL: https://github.com/llvm/llvm-project/commit/39124f525accda4002fd0a91dfe9c1d697709ad0
DIFF: https://github.com/llvm/llvm-project/commit/39124f525accda4002fd0a91dfe9c1d697709ad0.diff
LOG: [NFC][X86] Clang-format X86RecognizableInstr.cpp (#73278)
Added:
Modified:
llvm/utils/TableGen/X86RecognizableInstr.cpp
Removed:
################################################################################
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp
index bcfe7a749c09533..73afcdbfe882f21 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.cpp
+++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp
@@ -24,18 +24,19 @@
using namespace llvm;
using namespace X86Disassembler;
-std::string X86Disassembler::getMnemonic(const CodeGenInstruction *I, unsigned Variant) {
- std::string AsmString = I->FlattenAsmStringVariants(I->AsmString, Variant);
- StringRef Mnemonic(AsmString);
- // Extract a mnemonic assuming it's separated by \t
- Mnemonic = Mnemonic.take_until([](char C) { return C == '\t'; });
-
- // Special case: CMOVCC, JCC, SETCC have "${cond}" in mnemonic.
- // Replace it with "CC" in-place.
- size_t CondPos = Mnemonic.find("${cond}");
- if (CondPos != StringRef::npos)
- Mnemonic = AsmString.replace(CondPos, StringRef::npos, "CC");
- return Mnemonic.upper();
+std::string X86Disassembler::getMnemonic(const CodeGenInstruction *I,
+ unsigned Variant) {
+ std::string AsmString = I->FlattenAsmStringVariants(I->AsmString, Variant);
+ StringRef Mnemonic(AsmString);
+ // Extract a mnemonic assuming it's separated by \t
+ Mnemonic = Mnemonic.take_until([](char C) { return C == '\t'; });
+
+ // Special case: CMOVCC, JCC, SETCC have "${cond}" in mnemonic.
+ // Replace it with "CC" in-place.
+ size_t CondPos = Mnemonic.find("${cond}");
+ if (CondPos != StringRef::npos)
+ Mnemonic = AsmString.replace(CondPos, StringRef::npos, "CC");
+ return Mnemonic.upper();
}
bool X86Disassembler::isRegisterOperand(const Record *Rec) {
@@ -80,7 +81,7 @@ static uint8_t byteFromBitsInit(BitsInit &init) {
assert(width <= 8 && "Field is too large for uint8_t!");
- int index;
+ int index;
uint8_t mask = 0x01;
uint8_t ret = 0;
@@ -101,8 +102,8 @@ static uint8_t byteFromBitsInit(BitsInit &init) {
/// @param rec - The record from which to extract the value.
/// @param name - The name of the field in the record.
/// @return - The field, as translated by byteFromBitsInit().
-static uint8_t byteFromRec(const Record* rec, StringRef name) {
- BitsInit* bits = rec->getValueAsBitsInit(name);
+static uint8_t byteFromRec(const Record *rec, StringRef name) {
+ BitsInit *bits = rec->getValueAsBitsInit(name);
return byteFromBitsInit(*bits);
}
@@ -176,10 +177,13 @@ void RecognizableInstr::processInstr(DisassemblerTables &tables,
recogInstr.emitDecodePath(tables);
}
-#define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
- (HasEVEX_K && HasEVEX_B ? n##_K_B : \
- (HasEVEX_KZ ? n##_KZ : \
- (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
+#define EVEX_KB(n) \
+ (HasEVEX_KZ && HasEVEX_B \
+ ? n##_KZ_B \
+ : (HasEVEX_K && HasEVEX_B \
+ ? n##_K_B \
+ : (HasEVEX_KZ ? n##_KZ \
+ : (HasEVEX_K ? n##_K : (HasEVEX_B ? n##_B : n)))))
InstructionContext RecognizableInstr::insnContext() const {
InstructionContext insnContext;
@@ -245,8 +249,7 @@ InstructionContext RecognizableInstr::insnContext() const {
errs() << "Instruction does not use a prefix: " << Name << "\n";
llvm_unreachable("Invalid prefix");
}
- }
- else if (HasREX_W) {
+ } else if (HasREX_W) {
// VEX_W
if (OpPrefix == X86Local::PD)
insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
@@ -380,9 +383,9 @@ void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) {
// The scaling factor for AVX512 compressed displacement encoding is an
// instruction attribute. Adjust the ModRM encoding type to include the
// scale for compressed displacement.
- if ((encoding != ENCODING_RM &&
- encoding != ENCODING_VSIB &&
- encoding != ENCODING_SIB) ||CD8_Scale == 0)
+ if ((encoding != ENCODING_RM && encoding != ENCODING_VSIB &&
+ encoding != ENCODING_SIB) ||
+ CD8_Scale == 0)
return;
encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale));
assert(((encoding >= ENCODING_RM && encoding <= ENCODING_RM_CD64) ||
@@ -391,13 +394,11 @@ void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) {
"Invalid CDisp scaling");
}
-void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
- unsigned &physicalOperandIndex,
- unsigned numPhysicalOperands,
- const unsigned *operandMapping,
- OperandEncoding (*encodingFromString)
- (const std::string&,
- uint8_t OpSize)) {
+void RecognizableInstr::handleOperand(
+ bool optional, unsigned &operandIndex, unsigned &physicalOperandIndex,
+ unsigned numPhysicalOperands, const unsigned *operandMapping,
+ OperandEncoding (*encodingFromString)(const std::string &,
+ uint8_t OpSize)) {
if (optional) {
if (physicalOperandIndex >= numPhysicalOperands)
return;
@@ -408,7 +409,7 @@ void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
while (operandMapping[operandIndex] != operandIndex) {
Spec->operands[operandIndex].encoding = ENCODING_DUP;
Spec->operands[operandIndex].type =
- (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
+ (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
++operandIndex;
}
@@ -426,7 +427,7 @@ void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
}
void RecognizableInstr::emitInstructionSpecifier() {
- Spec->name = Name;
+ Spec->name = Name;
Spec->insnContext = insnContext();
@@ -438,12 +439,13 @@ void RecognizableInstr::emitInstructionSpecifier() {
// operandMapping maps from operands in OperandList to their originals.
// If operandMapping[i] != i, then the entry is a duplicate.
unsigned operandMapping[X86_MAX_OPERANDS];
- assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
+ assert(numOperands <= X86_MAX_OPERANDS &&
+ "X86_MAX_OPERANDS is not large enough");
for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
if (!OperandList[operandIndex].Constraints.empty()) {
const CGIOperandList::ConstraintInfo &Constraint =
- OperandList[operandIndex].Constraints[0];
+ OperandList[operandIndex].Constraints[0];
if (Constraint.isTied()) {
operandMapping[operandIndex] = operandIndex;
operandMapping[Constraint.getTiedOperand()] = operandIndex;
@@ -457,21 +459,14 @@ void RecognizableInstr::emitInstructionSpecifier() {
}
}
-#define HANDLE_OPERAND(class) \
- handleOperand(false, \
- operandIndex, \
- physicalOperandIndex, \
- numPhysicalOperands, \
- operandMapping, \
+#define HANDLE_OPERAND(class) \
+ handleOperand(false, operandIndex, physicalOperandIndex, \
+ numPhysicalOperands, operandMapping, \
class##EncodingFromString);
-#define HANDLE_OPTIONAL(class) \
- handleOperand(true, \
- operandIndex, \
- physicalOperandIndex, \
- numPhysicalOperands, \
- operandMapping, \
- class##EncodingFromString);
+#define HANDLE_OPTIONAL(class) \
+ handleOperand(true, operandIndex, physicalOperandIndex, numPhysicalOperands, \
+ operandMapping, class##EncodingFromString);
// operandIndex should always be < numOperands
unsigned operandIndex = 0;
@@ -489,7 +484,8 @@ void RecognizableInstr::emitInstructionSpecifier() {
#endif
switch (Form) {
- default: llvm_unreachable("Unhandled form");
+ default:
+ llvm_unreachable("Unhandled form");
case X86Local::PrefixByte:
return;
case X86Local::RawFrmSrc:
@@ -766,7 +762,7 @@ void RecognizableInstr::emitInstructionSpecifier() {
case X86Local::MRM6X:
case X86Local::MRM7X:
#define MAP(from, to) case X86Local::MRM_##from:
- X86_INSTR_MRM_MAPPING
+ X86_INSTR_MRM_MAPPING
#undef MAP
HANDLE_OPTIONAL(relocation)
break;
@@ -779,29 +775,53 @@ void RecognizableInstr::emitInstructionSpecifier() {
void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
// Special cases where the LLVM tables are not complete
-#define MAP(from, to) \
- case X86Local::MRM_##from:
+#define MAP(from, to) case X86Local::MRM_##from:
std::optional<OpcodeType> opcodeType;
switch (OpMap) {
- default: llvm_unreachable("Invalid map!");
- case X86Local::OB: opcodeType = ONEBYTE; break;
- case X86Local::TB: opcodeType = TWOBYTE; break;
- case X86Local::T8: opcodeType = THREEBYTE_38; break;
- case X86Local::TA: opcodeType = THREEBYTE_3A; break;
- case X86Local::XOP8: opcodeType = XOP8_MAP; break;
- case X86Local::XOP9: opcodeType = XOP9_MAP; break;
- case X86Local::XOPA: opcodeType = XOPA_MAP; break;
- case X86Local::ThreeDNow: opcodeType = THREEDNOW_MAP; break;
- case X86Local::T_MAP5: opcodeType = MAP5; break;
- case X86Local::T_MAP6: opcodeType = MAP6; break;
- case X86Local::T_MAP7: opcodeType = MAP7; break;
+ default:
+ llvm_unreachable("Invalid map!");
+ case X86Local::OB:
+ opcodeType = ONEBYTE;
+ break;
+ case X86Local::TB:
+ opcodeType = TWOBYTE;
+ break;
+ case X86Local::T8:
+ opcodeType = THREEBYTE_38;
+ break;
+ case X86Local::TA:
+ opcodeType = THREEBYTE_3A;
+ break;
+ case X86Local::XOP8:
+ opcodeType = XOP8_MAP;
+ break;
+ case X86Local::XOP9:
+ opcodeType = XOP9_MAP;
+ break;
+ case X86Local::XOPA:
+ opcodeType = XOPA_MAP;
+ break;
+ case X86Local::ThreeDNow:
+ opcodeType = THREEDNOW_MAP;
+ break;
+ case X86Local::T_MAP5:
+ opcodeType = MAP5;
+ break;
+ case X86Local::T_MAP6:
+ opcodeType = MAP6;
+ break;
+ case X86Local::T_MAP7:
+ opcodeType = MAP7;
+ break;
}
std::unique_ptr<ModRMFilter> filter;
switch (Form) {
- default: llvm_unreachable("Invalid form!");
- case X86Local::Pseudo: llvm_unreachable("Pseudo should not be emitted!");
+ default:
+ llvm_unreachable("Invalid form!");
+ case X86Local::Pseudo:
+ llvm_unreachable("Pseudo should not be emitted!");
case X86Local::RawFrm:
case X86Local::AddRegFrm:
case X86Local::RawFrmMemOffs:
@@ -835,28 +855,40 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
case X86Local::MRMXm:
filter = std::make_unique<ModFilter>(false);
break;
- case X86Local::MRM0r: case X86Local::MRM1r:
- case X86Local::MRM2r: case X86Local::MRM3r:
- case X86Local::MRM4r: case X86Local::MRM5r:
- case X86Local::MRM6r: case X86Local::MRM7r:
+ case X86Local::MRM0r:
+ case X86Local::MRM1r:
+ case X86Local::MRM2r:
+ case X86Local::MRM3r:
+ case X86Local::MRM4r:
+ case X86Local::MRM5r:
+ case X86Local::MRM6r:
+ case X86Local::MRM7r:
filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0r);
break;
- case X86Local::MRM0X: case X86Local::MRM1X:
- case X86Local::MRM2X: case X86Local::MRM3X:
- case X86Local::MRM4X: case X86Local::MRM5X:
- case X86Local::MRM6X: case X86Local::MRM7X:
+ case X86Local::MRM0X:
+ case X86Local::MRM1X:
+ case X86Local::MRM2X:
+ case X86Local::MRM3X:
+ case X86Local::MRM4X:
+ case X86Local::MRM5X:
+ case X86Local::MRM6X:
+ case X86Local::MRM7X:
filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0X);
break;
case X86Local::MRMr0:
filter = std::make_unique<ExtendedRMFilter>(true, Form - X86Local::MRMr0);
break;
- case X86Local::MRM0m: case X86Local::MRM1m:
- case X86Local::MRM2m: case X86Local::MRM3m:
- case X86Local::MRM4m: case X86Local::MRM5m:
- case X86Local::MRM6m: case X86Local::MRM7m:
+ case X86Local::MRM0m:
+ case X86Local::MRM1m:
+ case X86Local::MRM2m:
+ case X86Local::MRM3m:
+ case X86Local::MRM4m:
+ case X86Local::MRM5m:
+ case X86Local::MRM6m:
+ case X86Local::MRM7m:
filter = std::make_unique<ExtendedFilter>(false, Form - X86Local::MRM0m);
break;
- X86_INSTR_MRM_MAPPING
+ X86_INSTR_MRM_MAPPING
filter = std::make_unique<ExactFilter>(0xC0 + Form - X86Local::MRM_C0);
break;
} // switch (Form)
@@ -865,9 +897,15 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
unsigned AddressSize = 0;
switch (AdSize) {
- case X86Local::AdSize16: AddressSize = 16; break;
- case X86Local::AdSize32: AddressSize = 32; break;
- case X86Local::AdSize64: AddressSize = 64; break;
+ case X86Local::AdSize16:
+ AddressSize = 16;
+ break;
+ case X86Local::AdSize32:
+ AddressSize = 32;
+ break;
+ case X86Local::AdSize64:
+ AddressSize = 64;
+ break;
}
assert(opcodeType && "Opcode type not set");
@@ -886,8 +924,7 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
currentOpcode < (uint8_t)(opcodeToSet + Count); ++currentOpcode)
tables.setTableFields(*opcodeType, insnContext(), currentOpcode, *filter,
UID, Is32Bit, OpPrefix == 0,
- IgnoresVEX_L || EncodeRC,
- IgnoresW, AddressSize);
+ IgnoresVEX_L || EncodeRC, IgnoresW, AddressSize);
} else {
tables.setTableFields(*opcodeType, insnContext(), opcodeToSet, *filter, UID,
Is32Bit, OpPrefix == 0, IgnoresVEX_L || EncodeRC,
@@ -897,187 +934,190 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
#undef MAP
}
-#define TYPE(str, type) if (s == str) return type;
+#define TYPE(str, type) \
+ if (s == str) \
+ return type;
OperandType RecognizableInstr::typeFromString(const std::string &s,
- bool hasREX_W,
- uint8_t OpSize) {
- if(hasREX_W) {
+ bool hasREX_W, uint8_t OpSize) {
+ if (hasREX_W) {
// For instructions with a REX_W prefix, a declared 32-bit register encoding
// is special.
- TYPE("GR32", TYPE_R32)
+ TYPE("GR32", TYPE_R32)
}
- if(OpSize == X86Local::OpSize16) {
+ if (OpSize == X86Local::OpSize16) {
// For OpSize16 instructions, a declared 16-bit register or
// immediate encoding is special.
- TYPE("GR16", TYPE_Rv)
- } else if(OpSize == X86Local::OpSize32) {
+ TYPE("GR16", TYPE_Rv)
+ } else if (OpSize == X86Local::OpSize32) {
// For OpSize32 instructions, a declared 32-bit register or
// immediate encoding is special.
- TYPE("GR32", TYPE_Rv)
+ TYPE("GR32", TYPE_Rv)
}
- TYPE("i16mem", TYPE_M)
- TYPE("i16imm", TYPE_IMM)
- TYPE("i16i8imm", TYPE_IMM)
- TYPE("GR16", TYPE_R16)
- TYPE("GR16orGR32orGR64", TYPE_R16)
- TYPE("i32mem", TYPE_M)
- TYPE("i32imm", TYPE_IMM)
- TYPE("i32i8imm", TYPE_IMM)
- TYPE("GR32", TYPE_R32)
- TYPE("GR32orGR64", TYPE_R32)
- TYPE("i64mem", TYPE_M)
- TYPE("i64i32imm", TYPE_IMM)
- TYPE("i64i8imm", TYPE_IMM)
- TYPE("GR64", TYPE_R64)
- TYPE("i8mem", TYPE_M)
- TYPE("i8imm", TYPE_IMM)
- TYPE("u4imm", TYPE_UIMM8)
- TYPE("u8imm", TYPE_UIMM8)
- TYPE("i16u8imm", TYPE_UIMM8)
- TYPE("i32u8imm", TYPE_UIMM8)
- TYPE("i64u8imm", TYPE_UIMM8)
- TYPE("GR8", TYPE_R8)
- TYPE("VR128", TYPE_XMM)
- TYPE("VR128X", TYPE_XMM)
- TYPE("f128mem", TYPE_M)
- TYPE("f256mem", TYPE_M)
- TYPE("f512mem", TYPE_M)
- TYPE("FR128", TYPE_XMM)
- TYPE("FR64", TYPE_XMM)
- TYPE("FR64X", TYPE_XMM)
- TYPE("f64mem", TYPE_M)
- TYPE("sdmem", TYPE_M)
- TYPE("FR16X", TYPE_XMM)
- TYPE("FR32", TYPE_XMM)
- TYPE("FR32X", TYPE_XMM)
- TYPE("f32mem", TYPE_M)
- TYPE("f16mem", TYPE_M)
- TYPE("ssmem", TYPE_M)
- TYPE("shmem", TYPE_M)
- TYPE("RST", TYPE_ST)
- TYPE("RSTi", TYPE_ST)
- TYPE("i128mem", TYPE_M)
- TYPE("i256mem", TYPE_M)
- TYPE("i512mem", TYPE_M)
- TYPE("i512mem_GR16", TYPE_M)
- TYPE("i512mem_GR32", TYPE_M)
- TYPE("i512mem_GR64", TYPE_M)
- TYPE("i64i32imm_brtarget", TYPE_REL)
- TYPE("i16imm_brtarget", TYPE_REL)
- TYPE("i32imm_brtarget", TYPE_REL)
- TYPE("ccode", TYPE_IMM)
- TYPE("AVX512RC", TYPE_IMM)
- TYPE("brtarget32", TYPE_REL)
- TYPE("brtarget16", TYPE_REL)
- TYPE("brtarget8", TYPE_REL)
- TYPE("f80mem", TYPE_M)
- TYPE("lea64_32mem", TYPE_M)
- TYPE("lea64mem", TYPE_M)
- TYPE("VR64", TYPE_MM64)
- TYPE("i64imm", TYPE_IMM)
- TYPE("anymem", TYPE_M)
- TYPE("opaquemem", TYPE_M)
- TYPE("sibmem", TYPE_MSIB)
- TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
- TYPE("DEBUG_REG", TYPE_DEBUGREG)
- TYPE("CONTROL_REG", TYPE_CONTROLREG)
- TYPE("srcidx8", TYPE_SRCIDX)
- TYPE("srcidx16", TYPE_SRCIDX)
- TYPE("srcidx32", TYPE_SRCIDX)
- TYPE("srcidx64", TYPE_SRCIDX)
- TYPE("dstidx8", TYPE_DSTIDX)
- TYPE("dstidx16", TYPE_DSTIDX)
- TYPE("dstidx32", TYPE_DSTIDX)
- TYPE("dstidx64", TYPE_DSTIDX)
- TYPE("offset16_8", TYPE_MOFFS)
- TYPE("offset16_16", TYPE_MOFFS)
- TYPE("offset16_32", TYPE_MOFFS)
- TYPE("offset32_8", TYPE_MOFFS)
- TYPE("offset32_16", TYPE_MOFFS)
- TYPE("offset32_32", TYPE_MOFFS)
- TYPE("offset32_64", TYPE_MOFFS)
- TYPE("offset64_8", TYPE_MOFFS)
- TYPE("offset64_16", TYPE_MOFFS)
- TYPE("offset64_32", TYPE_MOFFS)
- TYPE("offset64_64", TYPE_MOFFS)
- TYPE("VR256", TYPE_YMM)
- TYPE("VR256X", TYPE_YMM)
- TYPE("VR512", TYPE_ZMM)
- TYPE("VK1", TYPE_VK)
- TYPE("VK1WM", TYPE_VK)
- TYPE("VK2", TYPE_VK)
- TYPE("VK2WM", TYPE_VK)
- TYPE("VK4", TYPE_VK)
- TYPE("VK4WM", TYPE_VK)
- TYPE("VK8", TYPE_VK)
- TYPE("VK8WM", TYPE_VK)
- TYPE("VK16", TYPE_VK)
- TYPE("VK16WM", TYPE_VK)
- TYPE("VK32", TYPE_VK)
- TYPE("VK32WM", TYPE_VK)
- TYPE("VK64", TYPE_VK)
- TYPE("VK64WM", TYPE_VK)
- TYPE("VK1Pair", TYPE_VK_PAIR)
- TYPE("VK2Pair", TYPE_VK_PAIR)
- TYPE("VK4Pair", TYPE_VK_PAIR)
- TYPE("VK8Pair", TYPE_VK_PAIR)
- TYPE("VK16Pair", TYPE_VK_PAIR)
- TYPE("vx64mem", TYPE_MVSIBX)
- TYPE("vx128mem", TYPE_MVSIBX)
- TYPE("vx256mem", TYPE_MVSIBX)
- TYPE("vy128mem", TYPE_MVSIBY)
- TYPE("vy256mem", TYPE_MVSIBY)
- TYPE("vx64xmem", TYPE_MVSIBX)
- TYPE("vx128xmem", TYPE_MVSIBX)
- TYPE("vx256xmem", TYPE_MVSIBX)
- TYPE("vy128xmem", TYPE_MVSIBY)
- TYPE("vy256xmem", TYPE_MVSIBY)
- TYPE("vy512xmem", TYPE_MVSIBY)
- TYPE("vz256mem", TYPE_MVSIBZ)
- TYPE("vz512mem", TYPE_MVSIBZ)
- TYPE("BNDR", TYPE_BNDR)
- TYPE("TILE", TYPE_TMM)
+ TYPE("i16mem", TYPE_M)
+ TYPE("i16imm", TYPE_IMM)
+ TYPE("i16i8imm", TYPE_IMM)
+ TYPE("GR16", TYPE_R16)
+ TYPE("GR16orGR32orGR64", TYPE_R16)
+ TYPE("i32mem", TYPE_M)
+ TYPE("i32imm", TYPE_IMM)
+ TYPE("i32i8imm", TYPE_IMM)
+ TYPE("GR32", TYPE_R32)
+ TYPE("GR32orGR64", TYPE_R32)
+ TYPE("i64mem", TYPE_M)
+ TYPE("i64i32imm", TYPE_IMM)
+ TYPE("i64i8imm", TYPE_IMM)
+ TYPE("GR64", TYPE_R64)
+ TYPE("i8mem", TYPE_M)
+ TYPE("i8imm", TYPE_IMM)
+ TYPE("u4imm", TYPE_UIMM8)
+ TYPE("u8imm", TYPE_UIMM8)
+ TYPE("i16u8imm", TYPE_UIMM8)
+ TYPE("i32u8imm", TYPE_UIMM8)
+ TYPE("i64u8imm", TYPE_UIMM8)
+ TYPE("GR8", TYPE_R8)
+ TYPE("VR128", TYPE_XMM)
+ TYPE("VR128X", TYPE_XMM)
+ TYPE("f128mem", TYPE_M)
+ TYPE("f256mem", TYPE_M)
+ TYPE("f512mem", TYPE_M)
+ TYPE("FR128", TYPE_XMM)
+ TYPE("FR64", TYPE_XMM)
+ TYPE("FR64X", TYPE_XMM)
+ TYPE("f64mem", TYPE_M)
+ TYPE("sdmem", TYPE_M)
+ TYPE("FR16X", TYPE_XMM)
+ TYPE("FR32", TYPE_XMM)
+ TYPE("FR32X", TYPE_XMM)
+ TYPE("f32mem", TYPE_M)
+ TYPE("f16mem", TYPE_M)
+ TYPE("ssmem", TYPE_M)
+ TYPE("shmem", TYPE_M)
+ TYPE("RST", TYPE_ST)
+ TYPE("RSTi", TYPE_ST)
+ TYPE("i128mem", TYPE_M)
+ TYPE("i256mem", TYPE_M)
+ TYPE("i512mem", TYPE_M)
+ TYPE("i512mem_GR16", TYPE_M)
+ TYPE("i512mem_GR32", TYPE_M)
+ TYPE("i512mem_GR64", TYPE_M)
+ TYPE("i64i32imm_brtarget", TYPE_REL)
+ TYPE("i16imm_brtarget", TYPE_REL)
+ TYPE("i32imm_brtarget", TYPE_REL)
+ TYPE("ccode", TYPE_IMM)
+ TYPE("AVX512RC", TYPE_IMM)
+ TYPE("brtarget32", TYPE_REL)
+ TYPE("brtarget16", TYPE_REL)
+ TYPE("brtarget8", TYPE_REL)
+ TYPE("f80mem", TYPE_M)
+ TYPE("lea64_32mem", TYPE_M)
+ TYPE("lea64mem", TYPE_M)
+ TYPE("VR64", TYPE_MM64)
+ TYPE("i64imm", TYPE_IMM)
+ TYPE("anymem", TYPE_M)
+ TYPE("opaquemem", TYPE_M)
+ TYPE("sibmem", TYPE_MSIB)
+ TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
+ TYPE("DEBUG_REG", TYPE_DEBUGREG)
+ TYPE("CONTROL_REG", TYPE_CONTROLREG)
+ TYPE("srcidx8", TYPE_SRCIDX)
+ TYPE("srcidx16", TYPE_SRCIDX)
+ TYPE("srcidx32", TYPE_SRCIDX)
+ TYPE("srcidx64", TYPE_SRCIDX)
+ TYPE("dstidx8", TYPE_DSTIDX)
+ TYPE("dstidx16", TYPE_DSTIDX)
+ TYPE("dstidx32", TYPE_DSTIDX)
+ TYPE("dstidx64", TYPE_DSTIDX)
+ TYPE("offset16_8", TYPE_MOFFS)
+ TYPE("offset16_16", TYPE_MOFFS)
+ TYPE("offset16_32", TYPE_MOFFS)
+ TYPE("offset32_8", TYPE_MOFFS)
+ TYPE("offset32_16", TYPE_MOFFS)
+ TYPE("offset32_32", TYPE_MOFFS)
+ TYPE("offset32_64", TYPE_MOFFS)
+ TYPE("offset64_8", TYPE_MOFFS)
+ TYPE("offset64_16", TYPE_MOFFS)
+ TYPE("offset64_32", TYPE_MOFFS)
+ TYPE("offset64_64", TYPE_MOFFS)
+ TYPE("VR256", TYPE_YMM)
+ TYPE("VR256X", TYPE_YMM)
+ TYPE("VR512", TYPE_ZMM)
+ TYPE("VK1", TYPE_VK)
+ TYPE("VK1WM", TYPE_VK)
+ TYPE("VK2", TYPE_VK)
+ TYPE("VK2WM", TYPE_VK)
+ TYPE("VK4", TYPE_VK)
+ TYPE("VK4WM", TYPE_VK)
+ TYPE("VK8", TYPE_VK)
+ TYPE("VK8WM", TYPE_VK)
+ TYPE("VK16", TYPE_VK)
+ TYPE("VK16WM", TYPE_VK)
+ TYPE("VK32", TYPE_VK)
+ TYPE("VK32WM", TYPE_VK)
+ TYPE("VK64", TYPE_VK)
+ TYPE("VK64WM", TYPE_VK)
+ TYPE("VK1Pair", TYPE_VK_PAIR)
+ TYPE("VK2Pair", TYPE_VK_PAIR)
+ TYPE("VK4Pair", TYPE_VK_PAIR)
+ TYPE("VK8Pair", TYPE_VK_PAIR)
+ TYPE("VK16Pair", TYPE_VK_PAIR)
+ TYPE("vx64mem", TYPE_MVSIBX)
+ TYPE("vx128mem", TYPE_MVSIBX)
+ TYPE("vx256mem", TYPE_MVSIBX)
+ TYPE("vy128mem", TYPE_MVSIBY)
+ TYPE("vy256mem", TYPE_MVSIBY)
+ TYPE("vx64xmem", TYPE_MVSIBX)
+ TYPE("vx128xmem", TYPE_MVSIBX)
+ TYPE("vx256xmem", TYPE_MVSIBX)
+ TYPE("vy128xmem", TYPE_MVSIBY)
+ TYPE("vy256xmem", TYPE_MVSIBY)
+ TYPE("vy512xmem", TYPE_MVSIBY)
+ TYPE("vz256mem", TYPE_MVSIBZ)
+ TYPE("vz512mem", TYPE_MVSIBZ)
+ TYPE("BNDR", TYPE_BNDR)
+ TYPE("TILE", TYPE_TMM)
errs() << "Unhandled type string " << s << "\n";
llvm_unreachable("Unhandled type string");
}
#undef TYPE
-#define ENCODING(str, encoding) if (s == str) return encoding;
+#define ENCODING(str, encoding) \
+ if (s == str) \
+ return encoding;
OperandEncoding
RecognizableInstr::immediateEncodingFromString(const std::string &s,
uint8_t OpSize) {
- if(OpSize != X86Local::OpSize16) {
+ if (OpSize != X86Local::OpSize16) {
// For instructions without an OpSize prefix, a declared 16-bit register or
// immediate encoding is special.
- ENCODING("i16imm", ENCODING_IW)
+ ENCODING("i16imm", ENCODING_IW)
}
- ENCODING("i32i8imm", ENCODING_IB)
- ENCODING("AVX512RC", ENCODING_IRC)
- ENCODING("i16imm", ENCODING_Iv)
- ENCODING("i16i8imm", ENCODING_IB)
- ENCODING("i32imm", ENCODING_Iv)
- ENCODING("i64i32imm", ENCODING_ID)
- ENCODING("i64i8imm", ENCODING_IB)
- ENCODING("i8imm", ENCODING_IB)
- ENCODING("u4imm", ENCODING_IB)
- ENCODING("u8imm", ENCODING_IB)
- ENCODING("i16u8imm", ENCODING_IB)
- ENCODING("i32u8imm", ENCODING_IB)
- ENCODING("i64u8imm", ENCODING_IB)
+ ENCODING("i32i8imm", ENCODING_IB)
+ ENCODING("AVX512RC", ENCODING_IRC)
+ ENCODING("i16imm", ENCODING_Iv)
+ ENCODING("i16i8imm", ENCODING_IB)
+ ENCODING("i32imm", ENCODING_Iv)
+ ENCODING("i64i32imm", ENCODING_ID)
+ ENCODING("i64i8imm", ENCODING_IB)
+ ENCODING("i8imm", ENCODING_IB)
+ ENCODING("u4imm", ENCODING_IB)
+ ENCODING("u8imm", ENCODING_IB)
+ ENCODING("i16u8imm", ENCODING_IB)
+ ENCODING("i32u8imm", ENCODING_IB)
+ ENCODING("i64u8imm", ENCODING_IB)
// This is not a typo. Instructions like BLENDVPD put
// register IDs in 8-bit immediates nowadays.
- ENCODING("FR32", ENCODING_IB)
- ENCODING("FR64", ENCODING_IB)
- ENCODING("FR128", ENCODING_IB)
- ENCODING("VR128", ENCODING_IB)
- ENCODING("VR256", ENCODING_IB)
- ENCODING("FR16X", ENCODING_IB)
- ENCODING("FR32X", ENCODING_IB)
- ENCODING("FR64X", ENCODING_IB)
- ENCODING("VR128X", ENCODING_IB)
- ENCODING("VR256X", ENCODING_IB)
- ENCODING("VR512", ENCODING_IB)
- ENCODING("TILE", ENCODING_IB)
+ ENCODING("FR32", ENCODING_IB)
+ ENCODING("FR64", ENCODING_IB)
+ ENCODING("FR128", ENCODING_IB)
+ ENCODING("VR128", ENCODING_IB)
+ ENCODING("VR256", ENCODING_IB)
+ ENCODING("FR16X", ENCODING_IB)
+ ENCODING("FR32X", ENCODING_IB)
+ ENCODING("FR64X", ENCODING_IB)
+ ENCODING("VR128X", ENCODING_IB)
+ ENCODING("VR256X", ENCODING_IB)
+ ENCODING("VR512", ENCODING_IB)
+ ENCODING("TILE", ENCODING_IB)
errs() << "Unhandled immediate encoding " << s << "\n";
llvm_unreachable("Unhandled immediate encoding");
}
@@ -1085,35 +1125,35 @@ RecognizableInstr::immediateEncodingFromString(const std::string &s,
OperandEncoding
RecognizableInstr::rmRegisterEncodingFromString(const std::string &s,
uint8_t OpSize) {
- ENCODING("RST", ENCODING_FP)
- ENCODING("RSTi", ENCODING_FP)
- ENCODING("GR16", ENCODING_RM)
- ENCODING("GR16orGR32orGR64",ENCODING_RM)
- ENCODING("GR32", ENCODING_RM)
- ENCODING("GR32orGR64", ENCODING_RM)
- ENCODING("GR64", ENCODING_RM)
- ENCODING("GR8", ENCODING_RM)
- ENCODING("VR128", ENCODING_RM)
- ENCODING("VR128X", ENCODING_RM)
- ENCODING("FR128", ENCODING_RM)
- ENCODING("FR64", ENCODING_RM)
- ENCODING("FR32", ENCODING_RM)
- ENCODING("FR64X", ENCODING_RM)
- ENCODING("FR32X", ENCODING_RM)
- ENCODING("FR16X", ENCODING_RM)
- ENCODING("VR64", ENCODING_RM)
- ENCODING("VR256", ENCODING_RM)
- ENCODING("VR256X", ENCODING_RM)
- ENCODING("VR512", ENCODING_RM)
- ENCODING("VK1", ENCODING_RM)
- ENCODING("VK2", ENCODING_RM)
- ENCODING("VK4", ENCODING_RM)
- ENCODING("VK8", ENCODING_RM)
- ENCODING("VK16", ENCODING_RM)
- ENCODING("VK32", ENCODING_RM)
- ENCODING("VK64", ENCODING_RM)
- ENCODING("BNDR", ENCODING_RM)
- ENCODING("TILE", ENCODING_RM)
+ ENCODING("RST", ENCODING_FP)
+ ENCODING("RSTi", ENCODING_FP)
+ ENCODING("GR16", ENCODING_RM)
+ ENCODING("GR16orGR32orGR64", ENCODING_RM)
+ ENCODING("GR32", ENCODING_RM)
+ ENCODING("GR32orGR64", ENCODING_RM)
+ ENCODING("GR64", ENCODING_RM)
+ ENCODING("GR8", ENCODING_RM)
+ ENCODING("VR128", ENCODING_RM)
+ ENCODING("VR128X", ENCODING_RM)
+ ENCODING("FR128", ENCODING_RM)
+ ENCODING("FR64", ENCODING_RM)
+ ENCODING("FR32", ENCODING_RM)
+ ENCODING("FR64X", ENCODING_RM)
+ ENCODING("FR32X", ENCODING_RM)
+ ENCODING("FR16X", ENCODING_RM)
+ ENCODING("VR64", ENCODING_RM)
+ ENCODING("VR256", ENCODING_RM)
+ ENCODING("VR256X", ENCODING_RM)
+ ENCODING("VR512", ENCODING_RM)
+ ENCODING("VK1", ENCODING_RM)
+ ENCODING("VK2", ENCODING_RM)
+ ENCODING("VK4", ENCODING_RM)
+ ENCODING("VK8", ENCODING_RM)
+ ENCODING("VK16", ENCODING_RM)
+ ENCODING("VK32", ENCODING_RM)
+ ENCODING("VK64", ENCODING_RM)
+ ENCODING("BNDR", ENCODING_RM)
+ ENCODING("TILE", ENCODING_RM)
errs() << "Unhandled R/M register encoding " << s << "\n";
llvm_unreachable("Unhandled R/M register encoding");
}
@@ -1121,48 +1161,48 @@ RecognizableInstr::rmRegisterEncodingFromString(const std::string &s,
OperandEncoding
RecognizableInstr::roRegisterEncodingFromString(const std::string &s,
uint8_t OpSize) {
- ENCODING("GR16", ENCODING_REG)
- ENCODING("GR16orGR32orGR64",ENCODING_REG)
- ENCODING("GR32", ENCODING_REG)
- ENCODING("GR32orGR64", ENCODING_REG)
- ENCODING("GR64", ENCODING_REG)
- ENCODING("GR8", ENCODING_REG)
- ENCODING("VR128", ENCODING_REG)
- ENCODING("FR128", ENCODING_REG)
- ENCODING("FR64", ENCODING_REG)
- ENCODING("FR32", ENCODING_REG)
- ENCODING("VR64", ENCODING_REG)
- ENCODING("SEGMENT_REG", ENCODING_REG)
- ENCODING("DEBUG_REG", ENCODING_REG)
- ENCODING("CONTROL_REG", ENCODING_REG)
- ENCODING("VR256", ENCODING_REG)
- ENCODING("VR256X", ENCODING_REG)
- ENCODING("VR128X", ENCODING_REG)
- ENCODING("FR64X", ENCODING_REG)
- ENCODING("FR32X", ENCODING_REG)
- ENCODING("FR16X", ENCODING_REG)
- ENCODING("VR512", ENCODING_REG)
- ENCODING("VK1", ENCODING_REG)
- ENCODING("VK2", ENCODING_REG)
- ENCODING("VK4", ENCODING_REG)
- ENCODING("VK8", ENCODING_REG)
- ENCODING("VK16", ENCODING_REG)
- ENCODING("VK32", ENCODING_REG)
- ENCODING("VK64", ENCODING_REG)
- ENCODING("VK1Pair", ENCODING_REG)
- ENCODING("VK2Pair", ENCODING_REG)
- ENCODING("VK4Pair", ENCODING_REG)
- ENCODING("VK8Pair", ENCODING_REG)
- ENCODING("VK16Pair", ENCODING_REG)
- ENCODING("VK1WM", ENCODING_REG)
- ENCODING("VK2WM", ENCODING_REG)
- ENCODING("VK4WM", ENCODING_REG)
- ENCODING("VK8WM", ENCODING_REG)
- ENCODING("VK16WM", ENCODING_REG)
- ENCODING("VK32WM", ENCODING_REG)
- ENCODING("VK64WM", ENCODING_REG)
- ENCODING("BNDR", ENCODING_REG)
- ENCODING("TILE", ENCODING_REG)
+ ENCODING("GR16", ENCODING_REG)
+ ENCODING("GR16orGR32orGR64", ENCODING_REG)
+ ENCODING("GR32", ENCODING_REG)
+ ENCODING("GR32orGR64", ENCODING_REG)
+ ENCODING("GR64", ENCODING_REG)
+ ENCODING("GR8", ENCODING_REG)
+ ENCODING("VR128", ENCODING_REG)
+ ENCODING("FR128", ENCODING_REG)
+ ENCODING("FR64", ENCODING_REG)
+ ENCODING("FR32", ENCODING_REG)
+ ENCODING("VR64", ENCODING_REG)
+ ENCODING("SEGMENT_REG", ENCODING_REG)
+ ENCODING("DEBUG_REG", ENCODING_REG)
+ ENCODING("CONTROL_REG", ENCODING_REG)
+ ENCODING("VR256", ENCODING_REG)
+ ENCODING("VR256X", ENCODING_REG)
+ ENCODING("VR128X", ENCODING_REG)
+ ENCODING("FR64X", ENCODING_REG)
+ ENCODING("FR32X", ENCODING_REG)
+ ENCODING("FR16X", ENCODING_REG)
+ ENCODING("VR512", ENCODING_REG)
+ ENCODING("VK1", ENCODING_REG)
+ ENCODING("VK2", ENCODING_REG)
+ ENCODING("VK4", ENCODING_REG)
+ ENCODING("VK8", ENCODING_REG)
+ ENCODING("VK16", ENCODING_REG)
+ ENCODING("VK32", ENCODING_REG)
+ ENCODING("VK64", ENCODING_REG)
+ ENCODING("VK1Pair", ENCODING_REG)
+ ENCODING("VK2Pair", ENCODING_REG)
+ ENCODING("VK4Pair", ENCODING_REG)
+ ENCODING("VK8Pair", ENCODING_REG)
+ ENCODING("VK16Pair", ENCODING_REG)
+ ENCODING("VK1WM", ENCODING_REG)
+ ENCODING("VK2WM", ENCODING_REG)
+ ENCODING("VK4WM", ENCODING_REG)
+ ENCODING("VK8WM", ENCODING_REG)
+ ENCODING("VK16WM", ENCODING_REG)
+ ENCODING("VK32WM", ENCODING_REG)
+ ENCODING("VK64WM", ENCODING_REG)
+ ENCODING("BNDR", ENCODING_REG)
+ ENCODING("TILE", ENCODING_REG)
errs() << "Unhandled reg/opcode register encoding " << s << "\n";
llvm_unreachable("Unhandled reg/opcode register encoding");
}
@@ -1170,27 +1210,27 @@ RecognizableInstr::roRegisterEncodingFromString(const std::string &s,
OperandEncoding
RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s,
uint8_t OpSize) {
- ENCODING("GR32", ENCODING_VVVV)
- ENCODING("GR64", ENCODING_VVVV)
- ENCODING("FR32", ENCODING_VVVV)
- ENCODING("FR128", ENCODING_VVVV)
- ENCODING("FR64", ENCODING_VVVV)
- ENCODING("VR128", ENCODING_VVVV)
- ENCODING("VR256", ENCODING_VVVV)
- ENCODING("FR16X", ENCODING_VVVV)
- ENCODING("FR32X", ENCODING_VVVV)
- ENCODING("FR64X", ENCODING_VVVV)
- ENCODING("VR128X", ENCODING_VVVV)
- ENCODING("VR256X", ENCODING_VVVV)
- ENCODING("VR512", ENCODING_VVVV)
- ENCODING("VK1", ENCODING_VVVV)
- ENCODING("VK2", ENCODING_VVVV)
- ENCODING("VK4", ENCODING_VVVV)
- ENCODING("VK8", ENCODING_VVVV)
- ENCODING("VK16", ENCODING_VVVV)
- ENCODING("VK32", ENCODING_VVVV)
- ENCODING("VK64", ENCODING_VVVV)
- ENCODING("TILE", ENCODING_VVVV)
+ ENCODING("GR32", ENCODING_VVVV)
+ ENCODING("GR64", ENCODING_VVVV)
+ ENCODING("FR32", ENCODING_VVVV)
+ ENCODING("FR128", ENCODING_VVVV)
+ ENCODING("FR64", ENCODING_VVVV)
+ ENCODING("VR128", ENCODING_VVVV)
+ ENCODING("VR256", ENCODING_VVVV)
+ ENCODING("FR16X", ENCODING_VVVV)
+ ENCODING("FR32X", ENCODING_VVVV)
+ ENCODING("FR64X", ENCODING_VVVV)
+ ENCODING("VR128X", ENCODING_VVVV)
+ ENCODING("VR256X", ENCODING_VVVV)
+ ENCODING("VR512", ENCODING_VVVV)
+ ENCODING("VK1", ENCODING_VVVV)
+ ENCODING("VK2", ENCODING_VVVV)
+ ENCODING("VK4", ENCODING_VVVV)
+ ENCODING("VK8", ENCODING_VVVV)
+ ENCODING("VK16", ENCODING_VVVV)
+ ENCODING("VK32", ENCODING_VVVV)
+ ENCODING("VK64", ENCODING_VVVV)
+ ENCODING("TILE", ENCODING_VVVV)
errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
llvm_unreachable("Unhandled VEX.vvvv register encoding");
}
@@ -1198,13 +1238,13 @@ RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s,
OperandEncoding
RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s,
uint8_t OpSize) {
- ENCODING("VK1WM", ENCODING_WRITEMASK)
- ENCODING("VK2WM", ENCODING_WRITEMASK)
- ENCODING("VK4WM", ENCODING_WRITEMASK)
- ENCODING("VK8WM", ENCODING_WRITEMASK)
- ENCODING("VK16WM", ENCODING_WRITEMASK)
- ENCODING("VK32WM", ENCODING_WRITEMASK)
- ENCODING("VK64WM", ENCODING_WRITEMASK)
+ ENCODING("VK1WM", ENCODING_WRITEMASK)
+ ENCODING("VK2WM", ENCODING_WRITEMASK)
+ ENCODING("VK4WM", ENCODING_WRITEMASK)
+ ENCODING("VK8WM", ENCODING_WRITEMASK)
+ ENCODING("VK16WM", ENCODING_WRITEMASK)
+ ENCODING("VK32WM", ENCODING_WRITEMASK)
+ ENCODING("VK64WM", ENCODING_WRITEMASK)
errs() << "Unhandled mask register encoding " << s << "\n";
llvm_unreachable("Unhandled mask register encoding");
}
@@ -1212,44 +1252,44 @@ RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s,
OperandEncoding
RecognizableInstr::memoryEncodingFromString(const std::string &s,
uint8_t OpSize) {
- ENCODING("i16mem", ENCODING_RM)
- ENCODING("i32mem", ENCODING_RM)
- ENCODING("i64mem", ENCODING_RM)
- ENCODING("i8mem", ENCODING_RM)
- ENCODING("shmem", ENCODING_RM)
- ENCODING("ssmem", ENCODING_RM)
- ENCODING("sdmem", ENCODING_RM)
- ENCODING("f128mem", ENCODING_RM)
- ENCODING("f256mem", ENCODING_RM)
- ENCODING("f512mem", ENCODING_RM)
- ENCODING("f64mem", ENCODING_RM)
- ENCODING("f32mem", ENCODING_RM)
- ENCODING("f16mem", ENCODING_RM)
- ENCODING("i128mem", ENCODING_RM)
- ENCODING("i256mem", ENCODING_RM)
- ENCODING("i512mem", ENCODING_RM)
- ENCODING("i512mem_GR16", ENCODING_RM)
- ENCODING("i512mem_GR32", ENCODING_RM)
- ENCODING("i512mem_GR64", ENCODING_RM)
- ENCODING("f80mem", ENCODING_RM)
- ENCODING("lea64_32mem", ENCODING_RM)
- ENCODING("lea64mem", ENCODING_RM)
- ENCODING("anymem", ENCODING_RM)
- ENCODING("opaquemem", ENCODING_RM)
- ENCODING("sibmem", ENCODING_SIB)
- ENCODING("vx64mem", ENCODING_VSIB)
- ENCODING("vx128mem", ENCODING_VSIB)
- ENCODING("vx256mem", ENCODING_VSIB)
- ENCODING("vy128mem", ENCODING_VSIB)
- ENCODING("vy256mem", ENCODING_VSIB)
- ENCODING("vx64xmem", ENCODING_VSIB)
- ENCODING("vx128xmem", ENCODING_VSIB)
- ENCODING("vx256xmem", ENCODING_VSIB)
- ENCODING("vy128xmem", ENCODING_VSIB)
- ENCODING("vy256xmem", ENCODING_VSIB)
- ENCODING("vy512xmem", ENCODING_VSIB)
- ENCODING("vz256mem", ENCODING_VSIB)
- ENCODING("vz512mem", ENCODING_VSIB)
+ ENCODING("i16mem", ENCODING_RM)
+ ENCODING("i32mem", ENCODING_RM)
+ ENCODING("i64mem", ENCODING_RM)
+ ENCODING("i8mem", ENCODING_RM)
+ ENCODING("shmem", ENCODING_RM)
+ ENCODING("ssmem", ENCODING_RM)
+ ENCODING("sdmem", ENCODING_RM)
+ ENCODING("f128mem", ENCODING_RM)
+ ENCODING("f256mem", ENCODING_RM)
+ ENCODING("f512mem", ENCODING_RM)
+ ENCODING("f64mem", ENCODING_RM)
+ ENCODING("f32mem", ENCODING_RM)
+ ENCODING("f16mem", ENCODING_RM)
+ ENCODING("i128mem", ENCODING_RM)
+ ENCODING("i256mem", ENCODING_RM)
+ ENCODING("i512mem", ENCODING_RM)
+ ENCODING("i512mem_GR16", ENCODING_RM)
+ ENCODING("i512mem_GR32", ENCODING_RM)
+ ENCODING("i512mem_GR64", ENCODING_RM)
+ ENCODING("f80mem", ENCODING_RM)
+ ENCODING("lea64_32mem", ENCODING_RM)
+ ENCODING("lea64mem", ENCODING_RM)
+ ENCODING("anymem", ENCODING_RM)
+ ENCODING("opaquemem", ENCODING_RM)
+ ENCODING("sibmem", ENCODING_SIB)
+ ENCODING("vx64mem", ENCODING_VSIB)
+ ENCODING("vx128mem", ENCODING_VSIB)
+ ENCODING("vx256mem", ENCODING_VSIB)
+ ENCODING("vy128mem", ENCODING_VSIB)
+ ENCODING("vy256mem", ENCODING_VSIB)
+ ENCODING("vx64xmem", ENCODING_VSIB)
+ ENCODING("vx128xmem", ENCODING_VSIB)
+ ENCODING("vx256xmem", ENCODING_VSIB)
+ ENCODING("vy128xmem", ENCODING_VSIB)
+ ENCODING("vy256xmem", ENCODING_VSIB)
+ ENCODING("vy512xmem", ENCODING_VSIB)
+ ENCODING("vz256mem", ENCODING_VSIB)
+ ENCODING("vz512mem", ENCODING_VSIB)
errs() << "Unhandled memory encoding " << s << "\n";
llvm_unreachable("Unhandled memory encoding");
}
@@ -1257,48 +1297,48 @@ RecognizableInstr::memoryEncodingFromString(const std::string &s,
OperandEncoding
RecognizableInstr::relocationEncodingFromString(const std::string &s,
uint8_t OpSize) {
- if(OpSize != X86Local::OpSize16) {
+ if (OpSize != X86Local::OpSize16) {
// For instructions without an OpSize prefix, a declared 16-bit register or
// immediate encoding is special.
- ENCODING("i16imm", ENCODING_IW)
+ ENCODING("i16imm", ENCODING_IW)
}
- ENCODING("i16imm", ENCODING_Iv)
- ENCODING("i16i8imm", ENCODING_IB)
- ENCODING("i32imm", ENCODING_Iv)
- ENCODING("i32i8imm", ENCODING_IB)
- ENCODING("i64i32imm", ENCODING_ID)
- ENCODING("i64i8imm", ENCODING_IB)
- ENCODING("i8imm", ENCODING_IB)
- ENCODING("u8imm", ENCODING_IB)
- ENCODING("i16u8imm", ENCODING_IB)
- ENCODING("i32u8imm", ENCODING_IB)
- ENCODING("i64u8imm", ENCODING_IB)
+ ENCODING("i16imm", ENCODING_Iv)
+ ENCODING("i16i8imm", ENCODING_IB)
+ ENCODING("i32imm", ENCODING_Iv)
+ ENCODING("i32i8imm", ENCODING_IB)
+ ENCODING("i64i32imm", ENCODING_ID)
+ ENCODING("i64i8imm", ENCODING_IB)
+ ENCODING("i8imm", ENCODING_IB)
+ ENCODING("u8imm", ENCODING_IB)
+ ENCODING("i16u8imm", ENCODING_IB)
+ ENCODING("i32u8imm", ENCODING_IB)
+ ENCODING("i64u8imm", ENCODING_IB)
ENCODING("i64i32imm_brtarget", ENCODING_ID)
- ENCODING("i16imm_brtarget", ENCODING_IW)
- ENCODING("i32imm_brtarget", ENCODING_ID)
- ENCODING("brtarget32", ENCODING_ID)
- ENCODING("brtarget16", ENCODING_IW)
- ENCODING("brtarget8", ENCODING_IB)
- ENCODING("i64imm", ENCODING_IO)
- ENCODING("offset16_8", ENCODING_Ia)
- ENCODING("offset16_16", ENCODING_Ia)
- ENCODING("offset16_32", ENCODING_Ia)
- ENCODING("offset32_8", ENCODING_Ia)
- ENCODING("offset32_16", ENCODING_Ia)
- ENCODING("offset32_32", ENCODING_Ia)
- ENCODING("offset32_64", ENCODING_Ia)
- ENCODING("offset64_8", ENCODING_Ia)
- ENCODING("offset64_16", ENCODING_Ia)
- ENCODING("offset64_32", ENCODING_Ia)
- ENCODING("offset64_64", ENCODING_Ia)
- ENCODING("srcidx8", ENCODING_SI)
- ENCODING("srcidx16", ENCODING_SI)
- ENCODING("srcidx32", ENCODING_SI)
- ENCODING("srcidx64", ENCODING_SI)
- ENCODING("dstidx8", ENCODING_DI)
- ENCODING("dstidx16", ENCODING_DI)
- ENCODING("dstidx32", ENCODING_DI)
- ENCODING("dstidx64", ENCODING_DI)
+ ENCODING("i16imm_brtarget", ENCODING_IW)
+ ENCODING("i32imm_brtarget", ENCODING_ID)
+ ENCODING("brtarget32", ENCODING_ID)
+ ENCODING("brtarget16", ENCODING_IW)
+ ENCODING("brtarget8", ENCODING_IB)
+ ENCODING("i64imm", ENCODING_IO)
+ ENCODING("offset16_8", ENCODING_Ia)
+ ENCODING("offset16_16", ENCODING_Ia)
+ ENCODING("offset16_32", ENCODING_Ia)
+ ENCODING("offset32_8", ENCODING_Ia)
+ ENCODING("offset32_16", ENCODING_Ia)
+ ENCODING("offset32_32", ENCODING_Ia)
+ ENCODING("offset32_64", ENCODING_Ia)
+ ENCODING("offset64_8", ENCODING_Ia)
+ ENCODING("offset64_16", ENCODING_Ia)
+ ENCODING("offset64_32", ENCODING_Ia)
+ ENCODING("offset64_64", ENCODING_Ia)
+ ENCODING("srcidx8", ENCODING_SI)
+ ENCODING("srcidx16", ENCODING_SI)
+ ENCODING("srcidx32", ENCODING_SI)
+ ENCODING("srcidx64", ENCODING_SI)
+ ENCODING("dstidx8", ENCODING_DI)
+ ENCODING("dstidx16", ENCODING_DI)
+ ENCODING("dstidx32", ENCODING_DI)
+ ENCODING("dstidx64", ENCODING_DI)
errs() << "Unhandled relocation encoding " << s << "\n";
llvm_unreachable("Unhandled relocation encoding");
}
@@ -1306,11 +1346,11 @@ RecognizableInstr::relocationEncodingFromString(const std::string &s,
OperandEncoding
RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s,
uint8_t OpSize) {
- ENCODING("GR32", ENCODING_Rv)
- ENCODING("GR64", ENCODING_RO)
- ENCODING("GR16", ENCODING_Rv)
- ENCODING("GR8", ENCODING_RB)
- ENCODING("ccode", ENCODING_CC)
+ ENCODING("GR32", ENCODING_Rv)
+ ENCODING("GR64", ENCODING_RO)
+ ENCODING("GR16", ENCODING_Rv)
+ ENCODING("GR8", ENCODING_RB)
+ ENCODING("ccode", ENCODING_CC)
errs() << "Unhandled opcode modifier encoding " << s << "\n";
llvm_unreachable("Unhandled opcode modifier encoding");
}
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