[llvm] [NFC][X86] Clang-format X86RecognizableInstr.cpp (PR #73278)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 23 19:44:32 PST 2023
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86
Author: Shengchen Kan (KanRobert)
<details>
<summary>Changes</summary>
---
Patch is 43.93 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/73278.diff
1 Files Affected:
- (modified) llvm/utils/TableGen/X86RecognizableInstr.cpp (+463-423)
``````````diff
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp
index bcfe7a749c09533..73afcdbfe882f21 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.cpp
+++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp
@@ -24,18 +24,19 @@
using namespace llvm;
using namespace X86Disassembler;
-std::string X86Disassembler::getMnemonic(const CodeGenInstruction *I, unsigned Variant) {
- std::string AsmString = I->FlattenAsmStringVariants(I->AsmString, Variant);
- StringRef Mnemonic(AsmString);
- // Extract a mnemonic assuming it's separated by \t
- Mnemonic = Mnemonic.take_until([](char C) { return C == '\t'; });
-
- // Special case: CMOVCC, JCC, SETCC have "${cond}" in mnemonic.
- // Replace it with "CC" in-place.
- size_t CondPos = Mnemonic.find("${cond}");
- if (CondPos != StringRef::npos)
- Mnemonic = AsmString.replace(CondPos, StringRef::npos, "CC");
- return Mnemonic.upper();
+std::string X86Disassembler::getMnemonic(const CodeGenInstruction *I,
+ unsigned Variant) {
+ std::string AsmString = I->FlattenAsmStringVariants(I->AsmString, Variant);
+ StringRef Mnemonic(AsmString);
+ // Extract a mnemonic assuming it's separated by \t
+ Mnemonic = Mnemonic.take_until([](char C) { return C == '\t'; });
+
+ // Special case: CMOVCC, JCC, SETCC have "${cond}" in mnemonic.
+ // Replace it with "CC" in-place.
+ size_t CondPos = Mnemonic.find("${cond}");
+ if (CondPos != StringRef::npos)
+ Mnemonic = AsmString.replace(CondPos, StringRef::npos, "CC");
+ return Mnemonic.upper();
}
bool X86Disassembler::isRegisterOperand(const Record *Rec) {
@@ -80,7 +81,7 @@ static uint8_t byteFromBitsInit(BitsInit &init) {
assert(width <= 8 && "Field is too large for uint8_t!");
- int index;
+ int index;
uint8_t mask = 0x01;
uint8_t ret = 0;
@@ -101,8 +102,8 @@ static uint8_t byteFromBitsInit(BitsInit &init) {
/// @param rec - The record from which to extract the value.
/// @param name - The name of the field in the record.
/// @return - The field, as translated by byteFromBitsInit().
-static uint8_t byteFromRec(const Record* rec, StringRef name) {
- BitsInit* bits = rec->getValueAsBitsInit(name);
+static uint8_t byteFromRec(const Record *rec, StringRef name) {
+ BitsInit *bits = rec->getValueAsBitsInit(name);
return byteFromBitsInit(*bits);
}
@@ -176,10 +177,13 @@ void RecognizableInstr::processInstr(DisassemblerTables &tables,
recogInstr.emitDecodePath(tables);
}
-#define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
- (HasEVEX_K && HasEVEX_B ? n##_K_B : \
- (HasEVEX_KZ ? n##_KZ : \
- (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
+#define EVEX_KB(n) \
+ (HasEVEX_KZ && HasEVEX_B \
+ ? n##_KZ_B \
+ : (HasEVEX_K && HasEVEX_B \
+ ? n##_K_B \
+ : (HasEVEX_KZ ? n##_KZ \
+ : (HasEVEX_K ? n##_K : (HasEVEX_B ? n##_B : n)))))
InstructionContext RecognizableInstr::insnContext() const {
InstructionContext insnContext;
@@ -245,8 +249,7 @@ InstructionContext RecognizableInstr::insnContext() const {
errs() << "Instruction does not use a prefix: " << Name << "\n";
llvm_unreachable("Invalid prefix");
}
- }
- else if (HasREX_W) {
+ } else if (HasREX_W) {
// VEX_W
if (OpPrefix == X86Local::PD)
insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
@@ -380,9 +383,9 @@ void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) {
// The scaling factor for AVX512 compressed displacement encoding is an
// instruction attribute. Adjust the ModRM encoding type to include the
// scale for compressed displacement.
- if ((encoding != ENCODING_RM &&
- encoding != ENCODING_VSIB &&
- encoding != ENCODING_SIB) ||CD8_Scale == 0)
+ if ((encoding != ENCODING_RM && encoding != ENCODING_VSIB &&
+ encoding != ENCODING_SIB) ||
+ CD8_Scale == 0)
return;
encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale));
assert(((encoding >= ENCODING_RM && encoding <= ENCODING_RM_CD64) ||
@@ -391,13 +394,11 @@ void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) {
"Invalid CDisp scaling");
}
-void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
- unsigned &physicalOperandIndex,
- unsigned numPhysicalOperands,
- const unsigned *operandMapping,
- OperandEncoding (*encodingFromString)
- (const std::string&,
- uint8_t OpSize)) {
+void RecognizableInstr::handleOperand(
+ bool optional, unsigned &operandIndex, unsigned &physicalOperandIndex,
+ unsigned numPhysicalOperands, const unsigned *operandMapping,
+ OperandEncoding (*encodingFromString)(const std::string &,
+ uint8_t OpSize)) {
if (optional) {
if (physicalOperandIndex >= numPhysicalOperands)
return;
@@ -408,7 +409,7 @@ void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
while (operandMapping[operandIndex] != operandIndex) {
Spec->operands[operandIndex].encoding = ENCODING_DUP;
Spec->operands[operandIndex].type =
- (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
+ (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
++operandIndex;
}
@@ -426,7 +427,7 @@ void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
}
void RecognizableInstr::emitInstructionSpecifier() {
- Spec->name = Name;
+ Spec->name = Name;
Spec->insnContext = insnContext();
@@ -438,12 +439,13 @@ void RecognizableInstr::emitInstructionSpecifier() {
// operandMapping maps from operands in OperandList to their originals.
// If operandMapping[i] != i, then the entry is a duplicate.
unsigned operandMapping[X86_MAX_OPERANDS];
- assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
+ assert(numOperands <= X86_MAX_OPERANDS &&
+ "X86_MAX_OPERANDS is not large enough");
for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
if (!OperandList[operandIndex].Constraints.empty()) {
const CGIOperandList::ConstraintInfo &Constraint =
- OperandList[operandIndex].Constraints[0];
+ OperandList[operandIndex].Constraints[0];
if (Constraint.isTied()) {
operandMapping[operandIndex] = operandIndex;
operandMapping[Constraint.getTiedOperand()] = operandIndex;
@@ -457,21 +459,14 @@ void RecognizableInstr::emitInstructionSpecifier() {
}
}
-#define HANDLE_OPERAND(class) \
- handleOperand(false, \
- operandIndex, \
- physicalOperandIndex, \
- numPhysicalOperands, \
- operandMapping, \
+#define HANDLE_OPERAND(class) \
+ handleOperand(false, operandIndex, physicalOperandIndex, \
+ numPhysicalOperands, operandMapping, \
class##EncodingFromString);
-#define HANDLE_OPTIONAL(class) \
- handleOperand(true, \
- operandIndex, \
- physicalOperandIndex, \
- numPhysicalOperands, \
- operandMapping, \
- class##EncodingFromString);
+#define HANDLE_OPTIONAL(class) \
+ handleOperand(true, operandIndex, physicalOperandIndex, numPhysicalOperands, \
+ operandMapping, class##EncodingFromString);
// operandIndex should always be < numOperands
unsigned operandIndex = 0;
@@ -489,7 +484,8 @@ void RecognizableInstr::emitInstructionSpecifier() {
#endif
switch (Form) {
- default: llvm_unreachable("Unhandled form");
+ default:
+ llvm_unreachable("Unhandled form");
case X86Local::PrefixByte:
return;
case X86Local::RawFrmSrc:
@@ -766,7 +762,7 @@ void RecognizableInstr::emitInstructionSpecifier() {
case X86Local::MRM6X:
case X86Local::MRM7X:
#define MAP(from, to) case X86Local::MRM_##from:
- X86_INSTR_MRM_MAPPING
+ X86_INSTR_MRM_MAPPING
#undef MAP
HANDLE_OPTIONAL(relocation)
break;
@@ -779,29 +775,53 @@ void RecognizableInstr::emitInstructionSpecifier() {
void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
// Special cases where the LLVM tables are not complete
-#define MAP(from, to) \
- case X86Local::MRM_##from:
+#define MAP(from, to) case X86Local::MRM_##from:
std::optional<OpcodeType> opcodeType;
switch (OpMap) {
- default: llvm_unreachable("Invalid map!");
- case X86Local::OB: opcodeType = ONEBYTE; break;
- case X86Local::TB: opcodeType = TWOBYTE; break;
- case X86Local::T8: opcodeType = THREEBYTE_38; break;
- case X86Local::TA: opcodeType = THREEBYTE_3A; break;
- case X86Local::XOP8: opcodeType = XOP8_MAP; break;
- case X86Local::XOP9: opcodeType = XOP9_MAP; break;
- case X86Local::XOPA: opcodeType = XOPA_MAP; break;
- case X86Local::ThreeDNow: opcodeType = THREEDNOW_MAP; break;
- case X86Local::T_MAP5: opcodeType = MAP5; break;
- case X86Local::T_MAP6: opcodeType = MAP6; break;
- case X86Local::T_MAP7: opcodeType = MAP7; break;
+ default:
+ llvm_unreachable("Invalid map!");
+ case X86Local::OB:
+ opcodeType = ONEBYTE;
+ break;
+ case X86Local::TB:
+ opcodeType = TWOBYTE;
+ break;
+ case X86Local::T8:
+ opcodeType = THREEBYTE_38;
+ break;
+ case X86Local::TA:
+ opcodeType = THREEBYTE_3A;
+ break;
+ case X86Local::XOP8:
+ opcodeType = XOP8_MAP;
+ break;
+ case X86Local::XOP9:
+ opcodeType = XOP9_MAP;
+ break;
+ case X86Local::XOPA:
+ opcodeType = XOPA_MAP;
+ break;
+ case X86Local::ThreeDNow:
+ opcodeType = THREEDNOW_MAP;
+ break;
+ case X86Local::T_MAP5:
+ opcodeType = MAP5;
+ break;
+ case X86Local::T_MAP6:
+ opcodeType = MAP6;
+ break;
+ case X86Local::T_MAP7:
+ opcodeType = MAP7;
+ break;
}
std::unique_ptr<ModRMFilter> filter;
switch (Form) {
- default: llvm_unreachable("Invalid form!");
- case X86Local::Pseudo: llvm_unreachable("Pseudo should not be emitted!");
+ default:
+ llvm_unreachable("Invalid form!");
+ case X86Local::Pseudo:
+ llvm_unreachable("Pseudo should not be emitted!");
case X86Local::RawFrm:
case X86Local::AddRegFrm:
case X86Local::RawFrmMemOffs:
@@ -835,28 +855,40 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
case X86Local::MRMXm:
filter = std::make_unique<ModFilter>(false);
break;
- case X86Local::MRM0r: case X86Local::MRM1r:
- case X86Local::MRM2r: case X86Local::MRM3r:
- case X86Local::MRM4r: case X86Local::MRM5r:
- case X86Local::MRM6r: case X86Local::MRM7r:
+ case X86Local::MRM0r:
+ case X86Local::MRM1r:
+ case X86Local::MRM2r:
+ case X86Local::MRM3r:
+ case X86Local::MRM4r:
+ case X86Local::MRM5r:
+ case X86Local::MRM6r:
+ case X86Local::MRM7r:
filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0r);
break;
- case X86Local::MRM0X: case X86Local::MRM1X:
- case X86Local::MRM2X: case X86Local::MRM3X:
- case X86Local::MRM4X: case X86Local::MRM5X:
- case X86Local::MRM6X: case X86Local::MRM7X:
+ case X86Local::MRM0X:
+ case X86Local::MRM1X:
+ case X86Local::MRM2X:
+ case X86Local::MRM3X:
+ case X86Local::MRM4X:
+ case X86Local::MRM5X:
+ case X86Local::MRM6X:
+ case X86Local::MRM7X:
filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0X);
break;
case X86Local::MRMr0:
filter = std::make_unique<ExtendedRMFilter>(true, Form - X86Local::MRMr0);
break;
- case X86Local::MRM0m: case X86Local::MRM1m:
- case X86Local::MRM2m: case X86Local::MRM3m:
- case X86Local::MRM4m: case X86Local::MRM5m:
- case X86Local::MRM6m: case X86Local::MRM7m:
+ case X86Local::MRM0m:
+ case X86Local::MRM1m:
+ case X86Local::MRM2m:
+ case X86Local::MRM3m:
+ case X86Local::MRM4m:
+ case X86Local::MRM5m:
+ case X86Local::MRM6m:
+ case X86Local::MRM7m:
filter = std::make_unique<ExtendedFilter>(false, Form - X86Local::MRM0m);
break;
- X86_INSTR_MRM_MAPPING
+ X86_INSTR_MRM_MAPPING
filter = std::make_unique<ExactFilter>(0xC0 + Form - X86Local::MRM_C0);
break;
} // switch (Form)
@@ -865,9 +897,15 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
unsigned AddressSize = 0;
switch (AdSize) {
- case X86Local::AdSize16: AddressSize = 16; break;
- case X86Local::AdSize32: AddressSize = 32; break;
- case X86Local::AdSize64: AddressSize = 64; break;
+ case X86Local::AdSize16:
+ AddressSize = 16;
+ break;
+ case X86Local::AdSize32:
+ AddressSize = 32;
+ break;
+ case X86Local::AdSize64:
+ AddressSize = 64;
+ break;
}
assert(opcodeType && "Opcode type not set");
@@ -886,8 +924,7 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
currentOpcode < (uint8_t)(opcodeToSet + Count); ++currentOpcode)
tables.setTableFields(*opcodeType, insnContext(), currentOpcode, *filter,
UID, Is32Bit, OpPrefix == 0,
- IgnoresVEX_L || EncodeRC,
- IgnoresW, AddressSize);
+ IgnoresVEX_L || EncodeRC, IgnoresW, AddressSize);
} else {
tables.setTableFields(*opcodeType, insnContext(), opcodeToSet, *filter, UID,
Is32Bit, OpPrefix == 0, IgnoresVEX_L || EncodeRC,
@@ -897,187 +934,190 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
#undef MAP
}
-#define TYPE(str, type) if (s == str) return type;
+#define TYPE(str, type) \
+ if (s == str) \
+ return type;
OperandType RecognizableInstr::typeFromString(const std::string &s,
- bool hasREX_W,
- uint8_t OpSize) {
- if(hasREX_W) {
+ bool hasREX_W, uint8_t OpSize) {
+ if (hasREX_W) {
// For instructions with a REX_W prefix, a declared 32-bit register encoding
// is special.
- TYPE("GR32", TYPE_R32)
+ TYPE("GR32", TYPE_R32)
}
- if(OpSize == X86Local::OpSize16) {
+ if (OpSize == X86Local::OpSize16) {
// For OpSize16 instructions, a declared 16-bit register or
// immediate encoding is special.
- TYPE("GR16", TYPE_Rv)
- } else if(OpSize == X86Local::OpSize32) {
+ TYPE("GR16", TYPE_Rv)
+ } else if (OpSize == X86Local::OpSize32) {
// For OpSize32 instructions, a declared 32-bit register or
// immediate encoding is special.
- TYPE("GR32", TYPE_Rv)
+ TYPE("GR32", TYPE_Rv)
}
- TYPE("i16mem", TYPE_M)
- TYPE("i16imm", TYPE_IMM)
- TYPE("i16i8imm", TYPE_IMM)
- TYPE("GR16", TYPE_R16)
- TYPE("GR16orGR32orGR64", TYPE_R16)
- TYPE("i32mem", TYPE_M)
- TYPE("i32imm", TYPE_IMM)
- TYPE("i32i8imm", TYPE_IMM)
- TYPE("GR32", TYPE_R32)
- TYPE("GR32orGR64", TYPE_R32)
- TYPE("i64mem", TYPE_M)
- TYPE("i64i32imm", TYPE_IMM)
- TYPE("i64i8imm", TYPE_IMM)
- TYPE("GR64", TYPE_R64)
- TYPE("i8mem", TYPE_M)
- TYPE("i8imm", TYPE_IMM)
- TYPE("u4imm", TYPE_UIMM8)
- TYPE("u8imm", TYPE_UIMM8)
- TYPE("i16u8imm", TYPE_UIMM8)
- TYPE("i32u8imm", TYPE_UIMM8)
- TYPE("i64u8imm", TYPE_UIMM8)
- TYPE("GR8", TYPE_R8)
- TYPE("VR128", TYPE_XMM)
- TYPE("VR128X", TYPE_XMM)
- TYPE("f128mem", TYPE_M)
- TYPE("f256mem", TYPE_M)
- TYPE("f512mem", TYPE_M)
- TYPE("FR128", TYPE_XMM)
- TYPE("FR64", TYPE_XMM)
- TYPE("FR64X", TYPE_XMM)
- TYPE("f64mem", TYPE_M)
- TYPE("sdmem", TYPE_M)
- TYPE("FR16X", TYPE_XMM)
- TYPE("FR32", TYPE_XMM)
- TYPE("FR32X", TYPE_XMM)
- TYPE("f32mem", TYPE_M)
- TYPE("f16mem", TYPE_M)
- TYPE("ssmem", TYPE_M)
- TYPE("shmem", TYPE_M)
- TYPE("RST", TYPE_ST)
- TYPE("RSTi", TYPE_ST)
- TYPE("i128mem", TYPE_M)
- TYPE("i256mem", TYPE_M)
- TYPE("i512mem", TYPE_M)
- TYPE("i512mem_GR16", TYPE_M)
- TYPE("i512mem_GR32", TYPE_M)
- TYPE("i512mem_GR64", TYPE_M)
- TYPE("i64i32imm_brtarget", TYPE_REL)
- TYPE("i16imm_brtarget", TYPE_REL)
- TYPE("i32imm_brtarget", TYPE_REL)
- TYPE("ccode", TYPE_IMM)
- TYPE("AVX512RC", TYPE_IMM)
- TYPE("brtarget32", TYPE_REL)
- TYPE("brtarget16", TYPE_REL)
- TYPE("brtarget8", TYPE_REL)
- TYPE("f80mem", TYPE_M)
- TYPE("lea64_32mem", TYPE_M)
- TYPE("lea64mem", TYPE_M)
- TYPE("VR64", TYPE_MM64)
- TYPE("i64imm", TYPE_IMM)
- TYPE("anymem", TYPE_M)
- TYPE("opaquemem", TYPE_M)
- TYPE("sibmem", TYPE_MSIB)
- TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
- TYPE("DEBUG_REG", TYPE_DEBUGREG)
- TYPE("CONTROL_REG", TYPE_CONTROLREG)
- TYPE("srcidx8", TYPE_SRCIDX)
- TYPE("srcidx16", TYPE_SRCIDX)
- TYPE("srcidx32", TYPE_SRCIDX)
- TYPE("srcidx64", TYPE_SRCIDX)
- TYPE("dstidx8", TYPE_DSTIDX)
- TYPE("dstidx16", TYPE_DSTIDX)
- TYPE("dstidx32", TYPE_DSTIDX)
- TYPE("dstidx64", TYPE_DSTIDX)
- TYPE("offset16_8", TYPE_MOFFS)
- TYPE("offset16_16", TYPE_MOFFS)
- TYPE("offset16_32", TYPE_MOFFS)
- TYPE("offset32_8", TYPE_MOFFS)
- TYPE("offset32_16", TYPE_MOFFS)
- TYPE("offset32_32", TYPE_MOFFS)
- TYPE("offset32_64", TYPE_MOFFS)
- TYPE("offset64_8", TYPE_MOFFS)
- TYPE("offset64_16", TYPE_MOFFS)
- TYPE("offset64_32", TYPE_MOFFS)
- TYPE("offset64_64", TYPE_MOFFS)
- TYPE("VR256", TYPE_YMM)
- TYPE("VR256X", TYPE_YMM)
- TYPE("VR512", TYPE_ZMM)
- TYPE("VK1", TYPE_VK)
- TYPE("VK1WM", TYPE_VK)
- TYPE("VK2", TYPE_VK)
- TYPE("VK2WM", TYPE_VK)
- TYPE("VK4", TYPE_VK)
- TYPE("VK4WM", TYPE_VK)
- TYPE("VK8", TYPE_VK)
- TYPE("VK8WM", TYPE_VK)
- TYPE("VK16", TYPE_VK)
- TYPE("VK16WM", TYPE_VK)
- TYPE("VK32", TYPE_VK)
- TYPE("VK32WM", TYPE_VK)
- TYPE("VK64", TYPE_VK)
- TYPE("VK64WM", TYPE_VK)
- TYPE("VK1Pair", TYPE_VK_PAIR)
- TYPE("VK2Pair", TYPE_VK_PAIR)
- TYPE("VK4Pair", TYPE_VK_PAIR)
- TYPE("VK8Pair", TYPE_VK_PAIR)
- TYPE("VK16Pair", TYPE_VK_PAIR)
- TYPE("vx64mem", TYPE_MVSIBX)
- TYPE("vx128mem", TYPE_MVSIBX)
- TYPE("vx256mem", TYPE_MVSIBX)
- TYPE("vy128mem", TYPE_MVSIBY)
- TYPE("vy256mem", TYPE_MVSIBY)
- TYPE("vx64xmem", TYPE_MVSIBX)
- TYPE("vx128xmem", TYPE_MVSIBX)
- TYPE("vx...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/73278
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