[llvm] [NFC][X86] Clang-format X86BaseInfo.h (PR #73274)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 23 18:13:59 PST 2023
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86
Author: Shengchen Kan (KanRobert)
<details>
<summary>Changes</summary>
---
Patch is 89.18 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/73274.diff
1 Files Affected:
- (modified) llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h (+1412-1248)
``````````diff
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h b/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
index c1b98d4a4740a5f..ece8cd9cc78047a 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
@@ -24,1297 +24,1461 @@
namespace llvm {
namespace X86 {
- // Enums for memory operand decoding. Each memory operand is represented with
- // a 5 operand sequence in the form:
- // [BaseReg, ScaleAmt, IndexReg, Disp, Segment]
- // These enums help decode this.
- enum {
- AddrBaseReg = 0,
- AddrScaleAmt = 1,
- AddrIndexReg = 2,
- AddrDisp = 3,
-
- /// AddrSegmentReg - The operand # of the segment in the memory operand.
- AddrSegmentReg = 4,
-
- /// AddrNumOperands - Total number of operands in a memory reference.
- AddrNumOperands = 5
- };
-
- /// AVX512 static rounding constants. These need to match the values in
- /// avx512fintrin.h.
- enum STATIC_ROUNDING {
- TO_NEAREST_INT = 0,
- TO_NEG_INF = 1,
- TO_POS_INF = 2,
- TO_ZERO = 3,
- CUR_DIRECTION = 4,
- NO_EXC = 8
- };
-
- /// The constants to describe instr prefixes if there are
- enum IPREFIXES {
- IP_NO_PREFIX = 0,
- IP_HAS_OP_SIZE = 1U << 0,
- IP_HAS_AD_SIZE = 1U << 1,
- IP_HAS_REPEAT_NE = 1U << 2,
- IP_HAS_REPEAT = 1U << 3,
- IP_HAS_LOCK = 1U << 4,
- IP_HAS_NOTRACK = 1U << 5,
- IP_USE_VEX = 1U << 6,
- IP_USE_VEX2 = 1U << 7,
- IP_USE_VEX3 = 1U << 8,
- IP_USE_EVEX = 1U << 9,
- IP_USE_DISP8 = 1U << 10,
- IP_USE_DISP32 = 1U << 11,
- };
-
- enum OperandType : unsigned {
- /// AVX512 embedded rounding control. This should only have values 0-3.
- OPERAND_ROUNDING_CONTROL = MCOI::OPERAND_FIRST_TARGET,
- OPERAND_COND_CODE,
- };
-
- // X86 specific condition code. These correspond to X86_*_COND in
- // X86InstrInfo.td. They must be kept in synch.
- enum CondCode {
- COND_O = 0,
- COND_NO = 1,
- COND_B = 2,
- COND_AE = 3,
- COND_E = 4,
- COND_NE = 5,
- COND_BE = 6,
- COND_A = 7,
- COND_S = 8,
- COND_NS = 9,
- COND_P = 10,
- COND_NP = 11,
- COND_L = 12,
- COND_GE = 13,
- COND_LE = 14,
- COND_G = 15,
- LAST_VALID_COND = COND_G,
-
- // Artificial condition codes. These are used by analyzeBranch
- // to indicate a block terminated with two conditional branches that together
- // form a compound condition. They occur in code using FCMP_OEQ or FCMP_UNE,
- // which can't be represented on x86 with a single condition. These
- // are never used in MachineInstrs and are inverses of one another.
- COND_NE_OR_P,
- COND_E_AND_NP,
-
- COND_INVALID
- };
-
- // The classification for the first instruction in macro fusion.
- enum class FirstMacroFusionInstKind {
- // TEST
- Test,
- // CMP
- Cmp,
- // AND
- And,
- // FIXME: Zen 3 support branch fusion for OR/XOR.
- // ADD, SUB
- AddSub,
- // INC, DEC
- IncDec,
- // Not valid as a first macro fusion instruction
- Invalid
- };
-
- enum class SecondMacroFusionInstKind {
- // JA, JB and variants.
- AB,
- // JE, JL, JG and variants.
- ELG,
- // JS, JP, JO and variants
- SPO,
- // Not a fusible jump.
- Invalid,
- };
-
- /// \returns the type of the first instruction in macro-fusion.
- inline FirstMacroFusionInstKind
- classifyFirstOpcodeInMacroFusion(unsigned Opcode) {
- switch (Opcode) {
- default:
- return FirstMacroFusionInstKind::Invalid;
- // TEST
- case X86::TEST16i16:
- case X86::TEST16mr:
- case X86::TEST16ri:
- case X86::TEST16rr:
- case X86::TEST32i32:
- case X86::TEST32mr:
- case X86::TEST32ri:
- case X86::TEST32rr:
- case X86::TEST64i32:
- case X86::TEST64mr:
- case X86::TEST64ri32:
- case X86::TEST64rr:
- case X86::TEST8i8:
- case X86::TEST8mr:
- case X86::TEST8ri:
- case X86::TEST8rr:
- return FirstMacroFusionInstKind::Test;
- case X86::AND16i16:
- case X86::AND16ri:
- case X86::AND16ri8:
- case X86::AND16rm:
- case X86::AND16rr:
- case X86::AND16rr_REV:
- case X86::AND32i32:
- case X86::AND32ri:
- case X86::AND32ri8:
- case X86::AND32rm:
- case X86::AND32rr:
- case X86::AND32rr_REV:
- case X86::AND64i32:
- case X86::AND64ri32:
- case X86::AND64ri8:
- case X86::AND64rm:
- case X86::AND64rr:
- case X86::AND64rr_REV:
- case X86::AND8i8:
- case X86::AND8ri:
- case X86::AND8ri8:
- case X86::AND8rm:
- case X86::AND8rr:
- case X86::AND8rr_REV:
- return FirstMacroFusionInstKind::And;
- // FIXME: Zen 3 support branch fusion for OR/XOR.
- // CMP
- case X86::CMP16i16:
- case X86::CMP16mr:
- case X86::CMP16ri:
- case X86::CMP16ri8:
- case X86::CMP16rm:
- case X86::CMP16rr:
- case X86::CMP16rr_REV:
- case X86::CMP32i32:
- case X86::CMP32mr:
- case X86::CMP32ri:
- case X86::CMP32ri8:
- case X86::CMP32rm:
- case X86::CMP32rr:
- case X86::CMP32rr_REV:
- case X86::CMP64i32:
- case X86::CMP64mr:
- case X86::CMP64ri32:
- case X86::CMP64ri8:
- case X86::CMP64rm:
- case X86::CMP64rr:
- case X86::CMP64rr_REV:
- case X86::CMP8i8:
- case X86::CMP8mr:
- case X86::CMP8ri:
- case X86::CMP8ri8:
- case X86::CMP8rm:
- case X86::CMP8rr:
- case X86::CMP8rr_REV:
- return FirstMacroFusionInstKind::Cmp;
- // ADD
- case X86::ADD16i16:
- case X86::ADD16ri:
- case X86::ADD16ri8:
- case X86::ADD16rm:
- case X86::ADD16rr:
- case X86::ADD16rr_REV:
- case X86::ADD32i32:
- case X86::ADD32ri:
- case X86::ADD32ri8:
- case X86::ADD32rm:
- case X86::ADD32rr:
- case X86::ADD32rr_REV:
- case X86::ADD64i32:
- case X86::ADD64ri32:
- case X86::ADD64ri8:
- case X86::ADD64rm:
- case X86::ADD64rr:
- case X86::ADD64rr_REV:
- case X86::ADD8i8:
- case X86::ADD8ri:
- case X86::ADD8ri8:
- case X86::ADD8rm:
- case X86::ADD8rr:
- case X86::ADD8rr_REV:
- // SUB
- case X86::SUB16i16:
- case X86::SUB16ri:
- case X86::SUB16ri8:
- case X86::SUB16rm:
- case X86::SUB16rr:
- case X86::SUB16rr_REV:
- case X86::SUB32i32:
- case X86::SUB32ri:
- case X86::SUB32ri8:
- case X86::SUB32rm:
- case X86::SUB32rr:
- case X86::SUB32rr_REV:
- case X86::SUB64i32:
- case X86::SUB64ri32:
- case X86::SUB64ri8:
- case X86::SUB64rm:
- case X86::SUB64rr:
- case X86::SUB64rr_REV:
- case X86::SUB8i8:
- case X86::SUB8ri:
- case X86::SUB8ri8:
- case X86::SUB8rm:
- case X86::SUB8rr:
- case X86::SUB8rr_REV:
- return FirstMacroFusionInstKind::AddSub;
- // INC
- case X86::INC16r:
- case X86::INC16r_alt:
- case X86::INC32r:
- case X86::INC32r_alt:
- case X86::INC64r:
- case X86::INC8r:
- // DEC
- case X86::DEC16r:
- case X86::DEC16r_alt:
- case X86::DEC32r:
- case X86::DEC32r_alt:
- case X86::DEC64r:
- case X86::DEC8r:
- return FirstMacroFusionInstKind::IncDec;
- }
+// Enums for memory operand decoding. Each memory operand is represented with
+// a 5 operand sequence in the form:
+// [BaseReg, ScaleAmt, IndexReg, Disp, Segment]
+// These enums help decode this.
+enum {
+ AddrBaseReg = 0,
+ AddrScaleAmt = 1,
+ AddrIndexReg = 2,
+ AddrDisp = 3,
+
+ /// AddrSegmentReg - The operand # of the segment in the memory operand.
+ AddrSegmentReg = 4,
+
+ /// AddrNumOperands - Total number of operands in a memory reference.
+ AddrNumOperands = 5
+};
+
+/// AVX512 static rounding constants. These need to match the values in
+/// avx512fintrin.h.
+enum STATIC_ROUNDING {
+ TO_NEAREST_INT = 0,
+ TO_NEG_INF = 1,
+ TO_POS_INF = 2,
+ TO_ZERO = 3,
+ CUR_DIRECTION = 4,
+ NO_EXC = 8
+};
+
+/// The constants to describe instr prefixes if there are
+enum IPREFIXES {
+ IP_NO_PREFIX = 0,
+ IP_HAS_OP_SIZE = 1U << 0,
+ IP_HAS_AD_SIZE = 1U << 1,
+ IP_HAS_REPEAT_NE = 1U << 2,
+ IP_HAS_REPEAT = 1U << 3,
+ IP_HAS_LOCK = 1U << 4,
+ IP_HAS_NOTRACK = 1U << 5,
+ IP_USE_VEX = 1U << 6,
+ IP_USE_VEX2 = 1U << 7,
+ IP_USE_VEX3 = 1U << 8,
+ IP_USE_EVEX = 1U << 9,
+ IP_USE_DISP8 = 1U << 10,
+ IP_USE_DISP32 = 1U << 11,
+};
+
+enum OperandType : unsigned {
+ /// AVX512 embedded rounding control. This should only have values 0-3.
+ OPERAND_ROUNDING_CONTROL = MCOI::OPERAND_FIRST_TARGET,
+ OPERAND_COND_CODE,
+};
+
+// X86 specific condition code. These correspond to X86_*_COND in
+// X86InstrInfo.td. They must be kept in synch.
+enum CondCode {
+ COND_O = 0,
+ COND_NO = 1,
+ COND_B = 2,
+ COND_AE = 3,
+ COND_E = 4,
+ COND_NE = 5,
+ COND_BE = 6,
+ COND_A = 7,
+ COND_S = 8,
+ COND_NS = 9,
+ COND_P = 10,
+ COND_NP = 11,
+ COND_L = 12,
+ COND_GE = 13,
+ COND_LE = 14,
+ COND_G = 15,
+ LAST_VALID_COND = COND_G,
+
+ // Artificial condition codes. These are used by analyzeBranch
+ // to indicate a block terminated with two conditional branches that together
+ // form a compound condition. They occur in code using FCMP_OEQ or FCMP_UNE,
+ // which can't be represented on x86 with a single condition. These
+ // are never used in MachineInstrs and are inverses of one another.
+ COND_NE_OR_P,
+ COND_E_AND_NP,
+
+ COND_INVALID
+};
+
+// The classification for the first instruction in macro fusion.
+enum class FirstMacroFusionInstKind {
+ // TEST
+ Test,
+ // CMP
+ Cmp,
+ // AND
+ And,
+ // FIXME: Zen 3 support branch fusion for OR/XOR.
+ // ADD, SUB
+ AddSub,
+ // INC, DEC
+ IncDec,
+ // Not valid as a first macro fusion instruction
+ Invalid
+};
+
+enum class SecondMacroFusionInstKind {
+ // JA, JB and variants.
+ AB,
+ // JE, JL, JG and variants.
+ ELG,
+ // JS, JP, JO and variants
+ SPO,
+ // Not a fusible jump.
+ Invalid,
+};
+
+/// \returns the type of the first instruction in macro-fusion.
+inline FirstMacroFusionInstKind
+classifyFirstOpcodeInMacroFusion(unsigned Opcode) {
+ switch (Opcode) {
+ default:
+ return FirstMacroFusionInstKind::Invalid;
+ // TEST
+ case X86::TEST16i16:
+ case X86::TEST16mr:
+ case X86::TEST16ri:
+ case X86::TEST16rr:
+ case X86::TEST32i32:
+ case X86::TEST32mr:
+ case X86::TEST32ri:
+ case X86::TEST32rr:
+ case X86::TEST64i32:
+ case X86::TEST64mr:
+ case X86::TEST64ri32:
+ case X86::TEST64rr:
+ case X86::TEST8i8:
+ case X86::TEST8mr:
+ case X86::TEST8ri:
+ case X86::TEST8rr:
+ return FirstMacroFusionInstKind::Test;
+ case X86::AND16i16:
+ case X86::AND16ri:
+ case X86::AND16ri8:
+ case X86::AND16rm:
+ case X86::AND16rr:
+ case X86::AND16rr_REV:
+ case X86::AND32i32:
+ case X86::AND32ri:
+ case X86::AND32ri8:
+ case X86::AND32rm:
+ case X86::AND32rr:
+ case X86::AND32rr_REV:
+ case X86::AND64i32:
+ case X86::AND64ri32:
+ case X86::AND64ri8:
+ case X86::AND64rm:
+ case X86::AND64rr:
+ case X86::AND64rr_REV:
+ case X86::AND8i8:
+ case X86::AND8ri:
+ case X86::AND8ri8:
+ case X86::AND8rm:
+ case X86::AND8rr:
+ case X86::AND8rr_REV:
+ return FirstMacroFusionInstKind::And;
+ // FIXME: Zen 3 support branch fusion for OR/XOR.
+ // CMP
+ case X86::CMP16i16:
+ case X86::CMP16mr:
+ case X86::CMP16ri:
+ case X86::CMP16ri8:
+ case X86::CMP16rm:
+ case X86::CMP16rr:
+ case X86::CMP16rr_REV:
+ case X86::CMP32i32:
+ case X86::CMP32mr:
+ case X86::CMP32ri:
+ case X86::CMP32ri8:
+ case X86::CMP32rm:
+ case X86::CMP32rr:
+ case X86::CMP32rr_REV:
+ case X86::CMP64i32:
+ case X86::CMP64mr:
+ case X86::CMP64ri32:
+ case X86::CMP64ri8:
+ case X86::CMP64rm:
+ case X86::CMP64rr:
+ case X86::CMP64rr_REV:
+ case X86::CMP8i8:
+ case X86::CMP8mr:
+ case X86::CMP8ri:
+ case X86::CMP8ri8:
+ case X86::CMP8rm:
+ case X86::CMP8rr:
+ case X86::CMP8rr_REV:
+ return FirstMacroFusionInstKind::Cmp;
+ // ADD
+ case X86::ADD16i16:
+ case X86::ADD16ri:
+ case X86::ADD16ri8:
+ case X86::ADD16rm:
+ case X86::ADD16rr:
+ case X86::ADD16rr_REV:
+ case X86::ADD32i32:
+ case X86::ADD32ri:
+ case X86::ADD32ri8:
+ case X86::ADD32rm:
+ case X86::ADD32rr:
+ case X86::ADD32rr_REV:
+ case X86::ADD64i32:
+ case X86::ADD64ri32:
+ case X86::ADD64ri8:
+ case X86::ADD64rm:
+ case X86::ADD64rr:
+ case X86::ADD64rr_REV:
+ case X86::ADD8i8:
+ case X86::ADD8ri:
+ case X86::ADD8ri8:
+ case X86::ADD8rm:
+ case X86::ADD8rr:
+ case X86::ADD8rr_REV:
+ // SUB
+ case X86::SUB16i16:
+ case X86::SUB16ri:
+ case X86::SUB16ri8:
+ case X86::SUB16rm:
+ case X86::SUB16rr:
+ case X86::SUB16rr_REV:
+ case X86::SUB32i32:
+ case X86::SUB32ri:
+ case X86::SUB32ri8:
+ case X86::SUB32rm:
+ case X86::SUB32rr:
+ case X86::SUB32rr_REV:
+ case X86::SUB64i32:
+ case X86::SUB64ri32:
+ case X86::SUB64ri8:
+ case X86::SUB64rm:
+ case X86::SUB64rr:
+ case X86::SUB64rr_REV:
+ case X86::SUB8i8:
+ case X86::SUB8ri:
+ case X86::SUB8ri8:
+ case X86::SUB8rm:
+ case X86::SUB8rr:
+ case X86::SUB8rr_REV:
+ return FirstMacroFusionInstKind::AddSub;
+ // INC
+ case X86::INC16r:
+ case X86::INC16r_alt:
+ case X86::INC32r:
+ case X86::INC32r_alt:
+ case X86::INC64r:
+ case X86::INC8r:
+ // DEC
+ case X86::DEC16r:
+ case X86::DEC16r_alt:
+ case X86::DEC32r:
+ case X86::DEC32r_alt:
+ case X86::DEC64r:
+ case X86::DEC8r:
+ return FirstMacroFusionInstKind::IncDec;
}
+}
- /// \returns the type of the second instruction in macro-fusion.
- inline SecondMacroFusionInstKind
- classifySecondCondCodeInMacroFusion(X86::CondCode CC) {
- if (CC == X86::COND_INVALID)
- return SecondMacroFusionInstKind::Invalid;
-
- switch (CC) {
- default:
- return SecondMacroFusionInstKind::Invalid;
- // JE,JZ
- case X86::COND_E:
- // JNE,JNZ
- case X86::COND_NE:
- // JL,JNGE
- case X86::COND_L:
- // JLE,JNG
- case X86::COND_LE:
- // JG,JNLE
- case X86::COND_G:
- // JGE,JNL
- case X86::COND_GE:
- return SecondMacroFusionInstKind::ELG;
- // JB,JC
- case X86::COND_B:
- // JNA,JBE
- case X86::COND_BE:
- // JA,JNBE
- case X86::COND_A:
- // JAE,JNC,JNB
- case X86::COND_AE:
- return SecondMacroFusionInstKind::AB;
- // JS
- case X86::COND_S:
- // JNS
- case X86::COND_NS:
- // JP,JPE
- case X86::COND_P:
- // JNP,JPO
- case X86::COND_NP:
- // JO
- case X86::COND_O:
- // JNO
- case X86::COND_NO:
- return SecondMacroFusionInstKind::SPO;
- }
+/// \returns the type of the second instruction in macro-fusion.
+inline SecondMacroFusionInstKind
+classifySecondCondCodeInMacroFusion(X86::CondCode CC) {
+ if (CC == X86::COND_INVALID)
+ return SecondMacroFusionInstKind::Invalid;
+
+ switch (CC) {
+ default:
+ return SecondMacroFusionInstKind::Invalid;
+ // JE,JZ
+ case X86::COND_E:
+ // JNE,JNZ
+ case X86::COND_NE:
+ // JL,JNGE
+ case X86::COND_L:
+ // JLE,JNG
+ case X86::COND_LE:
+ // JG,JNLE
+ case X86::COND_G:
+ // JGE,JNL
+ case X86::COND_GE:
+ return SecondMacroFusionInstKind::ELG;
+ // JB,JC
+ case X86::COND_B:
+ // JNA,JBE
+ case X86::COND_BE:
+ // JA,JNBE
+ case X86::COND_A:
+ // JAE,JNC,JNB
+ case X86::COND_AE:
+ return SecondMacroFusionInstKind::AB;
+ // JS
+ case X86::COND_S:
+ // JNS
+ case X86::COND_NS:
+ // JP,JPE
+ case X86::COND_P:
+ // JNP,JPO
+ case X86::COND_NP:
+ // JO
+ case X86::COND_O:
+ // JNO
+ case X86::COND_NO:
+ return SecondMacroFusionInstKind::SPO;
}
+}
- /// \param FirstKind kind of the first instruction in macro fusion.
- /// \param SecondKind kind of the second instruction in macro fusion.
- ///
- /// \returns true if the two instruction can be macro fused.
- inline bool isMacroFused(FirstMacroFusionInstKind FirstKind,
- SecondMacroFusionInstKind SecondKind) {
- switch (FirstKind) {
- case X86::FirstMacroFusionInstKind::Test:
- case X86::FirstMacroFusionInstKind::And:
- return true;
- case X86::FirstMacroFusionInstKind::Cmp:
- case X86::FirstMacroFusionInstKind::AddSub:
- return SecondKind == X86::SecondMacroFusionInstKind::AB ||
- SecondKind == X86::SecondMacroFusionInstKind::ELG;
- case X86::FirstMacroFusionInstKind::IncDec:
- return SecondKind == X86::SecondMacroFusionInstKind::ELG;
- case X86::FirstMacroFusionInstKind::Invalid:
- return false;
- }
- llvm_unreachable("unknown fusion type");
+/// \param FirstKind kind of the first instruction in macro fusion.
+/// \param SecondKind kind of the second instruction in macro fusion.
+///
+/// \returns true if the two instruction can be macro fused.
+inline bool isMacroFused(FirstMacroFusionInstKind FirstKind,
+ SecondMacroFusionInstKind SecondKind) {
+ switch (FirstKind) {
+ case X86::FirstMacroFusionInstKind::Test:
+ case X86::FirstMacroFusionInstKind::And:
+ return true;
+ case X86::FirstMacroFusionInstKind::Cmp:
+ case X86::FirstMacroFusionInstKind::AddSub:
+ return SecondKind == X86::SecondMacroFusionInstKind::AB ||
+ SecondKind == X86::SecondMacroFusionInstKind::ELG;
+ case X86::FirstMacroFusionInstKind::IncDec:
+ return SecondKind == X86::SecondMacroFusionInstKind::ELG;
+ case X86::FirstMacroFusionInstKind::Invalid:
+ return false;
}
+ llvm_unreachable("unknown fusion type");
+}
- /// Defines the possible values of the branch boundary alignment mask.
- enum AlignBranchBoundaryKind : uint8_t {
- AlignBranchNone = 0,
- AlignBranchFused = 1U << 0,
- AlignBranchJcc = 1U << 1,
- AlignBranchJmp = 1U << 2,
- AlignBranchCall = 1U << 3,
- AlignBranchRet = 1U << 4,
- AlignBranchIndirect = 1U << 5
- };
-
- /// Defines the encoding values for segment override prefix.
- enum EncodingOfSegmentOverridePrefix : uint8_t {
- CS_Encoding = 0x2E,
- DS_Encoding = 0x3E,
- ES_Encoding = 0x26,
- FS_Encoding = 0x64,
- GS_Encoding = 0x65,
- SS_Encoding = 0x36
- };
-
- /// Given a segment register, return the encoding of the segment override
- /// prefix for it.
- inline EncodingOfSegmentOverridePrefix
- getSegmentOverridePrefixForReg(unsigned Reg) {
- switch (Reg) {
- default:
- llvm_unreachable("Unknown segment register!");
- case X86::CS:
- return CS_Encoding;
- case X86::DS:
- return DS_Encoding;
- case X86::ES:
- return ES_Encoding;
- case X86::FS:
- return FS_Encoding;
- case X86::GS:
- return GS_Encoding;
- case X86::SS:
- return SS_Encoding;
- }
+/// Defines the possible values of the branch boundary alignment mask.
+enum AlignBranchBoundaryKind : uint8_t {
+ AlignBranchNone = 0,
+ AlignBranchFused = 1U << 0,
+ AlignBranchJcc = 1U << 1,
+ AlignBranchJmp = 1U << 2,
+ AlignBranchCall = 1U << 3,
+ AlignBranchRet = 1U << 4,
+ AlignBranchIndirect = 1U << 5
+};
+
+/// Defines the encoding values for segment override prefix.
+enum EncodingOfSegmentOverridePrefix : uint8_t {
+ CS_Encoding = 0x2E,
+ DS_Encoding = 0x3E,
+ ES_Encoding = 0x26,
+ FS_Encoding = 0x64,
+ GS_Encoding = 0x65,
+ SS_Encoding = 0x36
+};
+
+/// Given a segment register, return the encoding of the segment override
+/// prefix for it.
+inline EncodingOfSegmentOverridePrefix
+getSegmentOverridePrefixForReg(unsigned Reg) {
+ switch (Reg) {
+ default:
+ llvm_unreachable("Unknown segment register!");
+ case X86::CS:
+ return CS_Encoding;
+ case X86::DS:
+ return DS_Encoding;
+ case X86::ES:
+ return ES_Encoding;
+ case X86::FS:
+ return FS_Encoding;
+ case X86::GS:
+ return GS_Encoding;
+ case X86::SS:
+ return SS_Encoding;
}
+}
-} // end namespace X86;
+} // namespace X86
/// X86II - This namespace holds all of the target specific flags that
/// instruction info tracks.
///
namespace X86II {
- /// Target Operand Flag enum.
- enum TOF {
- //===------------------------------------------------------------------===//
- // X86 Specific MachineOperand flags.
-
- MO_NO_FLAG,
-
- /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
- /// relocation of:
- /// SYMBOL_LABEL + [. - PICBASELABEL]
- MO_GOT_ABSOLUTE_ADDRESS,
-
- /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
- /// immediate should get the value of the symbol minus the PIC base label:
- /// SYMBOL_LABEL - PICBASELABEL
- MO_PIC_BASE_OFFSET,
-
- /// MO_GOT - On a symbol operand this indicates that the immediate is the
- /// offset to the GOT entry for the symbol name from the base of the GOT.
- ///
...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/73274
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