[llvm] [X86] X86DAGToDAGISel - attempt to merge XMM/YMM loads with YMM/ZMM loads of the same ptr (PR #73126)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 23 02:42:40 PST 2023
================
@@ -1036,6 +1036,42 @@ void X86DAGToDAGISel::PreprocessISelDAG() {
break;
}
+ case ISD::LOAD: {
+ // If this is a XMM/YMM load of the same lower bits as another YMM/ZMM
+ // load, then just extract the lower subvector and avoid the second load.
+ auto *Ld = cast<LoadSDNode>(N);
+ MVT VT = N->getSimpleValueType(0);
+ if (ISD::isNormalLoad(Ld) && Ld->isSimple() &&
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RKSimon wrote:
If we do that then we'd probably need to ensure `Ld->isAtomic() == UserLd->isAtomic()` - would that be acceptable?
https://github.com/llvm/llvm-project/pull/73126
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