[llvm] [X86] X86DAGToDAGISel - attempt to merge XMM/YMM loads with YMM/ZMM loads of the same ptr (PR #73126)

[Shengchen Kan via llvm-commits]

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@@ -1036,6 +1036,42 @@ void X86DAGToDAGISel::PreprocessISelDAG() {
 
       break;
     }
+    case ISD::LOAD: {
+      // If this is a XMM/YMM load of the same lower bits as another YMM/ZMM
+      // load, then just extract the lower subvector and avoid the second load.
+      auto *Ld = cast<LoadSDNode>(N);
+      MVT VT = N->getSimpleValueType(0);
+      if (ISD::isNormalLoad(Ld) && Ld->isSimple() &&
+          (VT.is128BitVector() || VT.is256BitVector())) {
+        SDValue Ptr = Ld->getBasePtr();
+        SDValue Chain = Ld->getChain();
+        for (SDNode *User : Ptr->uses()) {
+          auto *UserLd = dyn_cast<LoadSDNode>(N);
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KanRobert wrote:

If the store changes the value for the second load, I think they will not have the same chain.

https://github.com/llvm/llvm-project/pull/73126