[llvm] a845061 - [AArch64] Use the same fast math preservation for MachineCombiner reassociation as X86/PowerPC/RISCV. (#72820)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 22 14:17:49 PST 2023
Author: Craig Topper
Date: 2023-11-22T14:17:45-08:00
New Revision: a8450619358c3de23b72aef7c1fd932bca112257
URL: https://github.com/llvm/llvm-project/commit/a8450619358c3de23b72aef7c1fd932bca112257
DIFF: https://github.com/llvm/llvm-project/commit/a8450619358c3de23b72aef7c1fd932bca112257.diff
LOG: [AArch64] Use the same fast math preservation for MachineCombiner reassociation as X86/PowerPC/RISCV. (#72820)
Don't blindly copy the original flags from the pre-reassociated
instrutions.
This copied the integer poison flags which are not safe to preserve
after reassociation.
For the FP flags, I think we should only keep the intersection of
the flags. Override setSpecialOperandAttr to do this.
Fixes #72777.
Added:
llvm/test/CodeGen/AArch64/pr72777.ll
Modified:
llvm/lib/CodeGen/TargetInstrInfo.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.h
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.h
llvm/lib/Target/X86/X86InstrInfo.cpp
llvm/test/CodeGen/AArch64/machine-combiner-reassociate.mir
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 5ede36505b5b00c..4e4c43a19d11267 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -1122,8 +1122,7 @@ void TargetInstrInfo::reassociateOps(
MachineInstrBuilder MIB1 =
BuildMI(*MF, MIMetadata(Prev), TII->get(NewPrevOpc), NewVR)
.addReg(RegX, getKillRegState(KillX))
- .addReg(RegY, getKillRegState(KillY))
- .setMIFlags(Prev.getFlags());
+ .addReg(RegY, getKillRegState(KillY));
if (SwapRootOperands) {
std::swap(RegA, NewVR);
@@ -1133,8 +1132,21 @@ void TargetInstrInfo::reassociateOps(
MachineInstrBuilder MIB2 =
BuildMI(*MF, MIMetadata(Root), TII->get(NewRootOpc), RegC)
.addReg(RegA, getKillRegState(KillA))
- .addReg(NewVR, getKillRegState(KillNewVR))
- .setMIFlags(Root.getFlags());
+ .addReg(NewVR, getKillRegState(KillNewVR));
+
+ // Propagate FP flags from the original instructions.
+ // But clear poison-generating flags because those may not be valid now.
+ // TODO: There should be a helper function for copying only fast-math-flags.
+ uint32_t IntersectedFlags = Root.getFlags() & Prev.getFlags();
+ MIB1->setFlags(IntersectedFlags);
+ MIB1->clearFlag(MachineInstr::MIFlag::NoSWrap);
+ MIB1->clearFlag(MachineInstr::MIFlag::NoUWrap);
+ MIB1->clearFlag(MachineInstr::MIFlag::IsExact);
+
+ MIB2->setFlags(IntersectedFlags);
+ MIB2->clearFlag(MachineInstr::MIFlag::NoSWrap);
+ MIB2->clearFlag(MachineInstr::MIFlag::NoUWrap);
+ MIB2->clearFlag(MachineInstr::MIFlag::IsExact);
setSpecialOperandAttr(Root, Prev, *MIB1, *MIB2);
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index c9e094a1588500c..c9c7dc886253c39 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -218,26 +218,6 @@ int PPCInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
return Latency;
}
-/// This is an architecture-specific helper function of reassociateOps.
-/// Set special operand attributes for new instructions after reassociation.
-void PPCInstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
- MachineInstr &OldMI2,
- MachineInstr &NewMI1,
- MachineInstr &NewMI2) const {
- // Propagate FP flags from the original instructions.
- // But clear poison-generating flags because those may not be valid now.
- uint32_t IntersectedFlags = OldMI1.getFlags() & OldMI2.getFlags();
- NewMI1.setFlags(IntersectedFlags);
- NewMI1.clearFlag(MachineInstr::MIFlag::NoSWrap);
- NewMI1.clearFlag(MachineInstr::MIFlag::NoUWrap);
- NewMI1.clearFlag(MachineInstr::MIFlag::IsExact);
-
- NewMI2.setFlags(IntersectedFlags);
- NewMI2.clearFlag(MachineInstr::MIFlag::NoSWrap);
- NewMI2.clearFlag(MachineInstr::MIFlag::NoUWrap);
- NewMI2.clearFlag(MachineInstr::MIFlag::IsExact);
-}
-
void PPCInstrInfo::setSpecialOperandAttr(MachineInstr &MI,
uint32_t Flags) const {
MI.setFlags(Flags);
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
index 1f59e994d9cb1ad..19c83e0a79dc44c 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
@@ -367,10 +367,6 @@ class PPCInstrInfo : public PPCGenInstrInfo {
/// perserved for more FMA chain reassociations on PowerPC.
int getExtendResourceLenLimit() const override { return 1; }
- void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
- MachineInstr &NewMI1,
- MachineInstr &NewMI2) const override;
-
// PowerPC specific version of setSpecialOperandAttr that copies Flags to MI
// and clears nuw, nsw, and exact flags.
void setSpecialOperandAttr(MachineInstr &MI, uint32_t Flags) const;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index a8ec93c3d5069f0..c76a330b08aa8fd 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1610,24 +1610,6 @@ MachineTraceStrategy RISCVInstrInfo::getMachineCombinerTraceStrategy() const {
return ForceMachineCombinerStrategy;
}
-void RISCVInstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
- MachineInstr &OldMI2,
- MachineInstr &NewMI1,
- MachineInstr &NewMI2) const {
- // Propagate FP flags from the original instructions.
- // But clear poison-generating flags because those may not be valid now.
- uint32_t IntersectedFlags = OldMI1.getFlags() & OldMI2.getFlags();
- NewMI1.setFlags(IntersectedFlags);
- NewMI1.clearFlag(MachineInstr::MIFlag::NoSWrap);
- NewMI1.clearFlag(MachineInstr::MIFlag::NoUWrap);
- NewMI1.clearFlag(MachineInstr::MIFlag::IsExact);
-
- NewMI2.setFlags(IntersectedFlags);
- NewMI2.clearFlag(MachineInstr::MIFlag::NoSWrap);
- NewMI2.clearFlag(MachineInstr::MIFlag::NoUWrap);
- NewMI2.clearFlag(MachineInstr::MIFlag::IsExact);
-}
-
void RISCVInstrInfo::finalizeInsInstrs(
MachineInstr &Root, MachineCombinerPattern &P,
SmallVectorImpl<MachineInstr *> &InsInstrs) const {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index c2bffe1f9d6a1bf..0eac8d1e1b1af2c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -224,9 +224,6 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
MachineTraceStrategy getMachineCombinerTraceStrategy() const override;
- void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
- MachineInstr &NewMI1,
- MachineInstr &NewMI2) const override;
bool
getMachineCombinerPatterns(MachineInstr &Root,
SmallVectorImpl<MachineCombinerPattern> &Patterns,
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 3ca7b427ae2067f..85977c1b9f1b6c5 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -9597,20 +9597,6 @@ void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
MachineInstr &OldMI2,
MachineInstr &NewMI1,
MachineInstr &NewMI2) const {
- // Propagate FP flags from the original instructions.
- // But clear poison-generating flags because those may not be valid now.
- // TODO: There should be a helper function for copying only fast-math-flags.
- uint32_t IntersectedFlags = OldMI1.getFlags() & OldMI2.getFlags();
- NewMI1.setFlags(IntersectedFlags);
- NewMI1.clearFlag(MachineInstr::MIFlag::NoSWrap);
- NewMI1.clearFlag(MachineInstr::MIFlag::NoUWrap);
- NewMI1.clearFlag(MachineInstr::MIFlag::IsExact);
-
- NewMI2.setFlags(IntersectedFlags);
- NewMI2.clearFlag(MachineInstr::MIFlag::NoSWrap);
- NewMI2.clearFlag(MachineInstr::MIFlag::NoUWrap);
- NewMI2.clearFlag(MachineInstr::MIFlag::IsExact);
-
// Integer instructions may define an implicit EFLAGS dest register operand.
MachineOperand *OldFlagDef1 = OldMI1.findRegisterDefOperand(X86::EFLAGS);
MachineOperand *OldFlagDef2 = OldMI2.findRegisterDefOperand(X86::EFLAGS);
diff --git a/llvm/test/CodeGen/AArch64/machine-combiner-reassociate.mir b/llvm/test/CodeGen/AArch64/machine-combiner-reassociate.mir
index 4a2fc7e87bb99a3..525f6dd05c6c658 100644
--- a/llvm/test/CodeGen/AArch64/machine-combiner-reassociate.mir
+++ b/llvm/test/CodeGen/AArch64/machine-combiner-reassociate.mir
@@ -91,11 +91,11 @@ body: |
# Check that flags on the instructions are preserved after reassociation.
# CHECK-LABEL: name: fadd_flags
-# CHECK: [[ADD1:%[0-9]+]]:fpr32 = nsz FADDSrr %0, %1, implicit $fpcr
-# CHECK-SAFE-NEXT: [[ADD2:%[0-9]+]]:fpr32 = nnan FADDSrr killed [[ADD1]], %2, implicit $fpcr
-# CHECK-SAFE-NEXT: [[ADD3:%[0-9]+]]:fpr32 = ninf FADDSrr killed [[ADD2]], %3, implicit $fpcr
-# CHECK-UNSAFE-NEXT: [[ADD2:%[0-9]+]]:fpr32 = nnan FADDSrr %2, %3, implicit $fpcr
-# CHECK-UNSAFE-NEXT: [[ADD3:%[0-9]+]]:fpr32 = ninf FADDSrr killed [[ADD1]], killed [[ADD2]], implicit $fpcr
+# CHECK: [[ADD1:%[0-9]+]]:fpr32 = nnan ninf nsz FADDSrr %0, %1, implicit $fpcr
+# CHECK-SAFE-NEXT: [[ADD2:%[0-9]+]]:fpr32 = nnan nsz FADDSrr killed [[ADD1]], %2, implicit $fpcr
+# CHECK-SAFE-NEXT: [[ADD3:%[0-9]+]]:fpr32 = ninf nsz FADDSrr killed [[ADD2]], %3, implicit $fpcr
+# CHECK-UNSAFE-NEXT: [[ADD2:%[0-9]+]]:fpr32 = nsz FADDSrr %2, %3, implicit $fpcr
+# CHECK-UNSAFE-NEXT: [[ADD3:%[0-9]+]]:fpr32 = nsz FADDSrr killed [[ADD1]], killed [[ADD2]], implicit $fpcr
---
name: fadd_flags
alignment: 4
@@ -125,8 +125,8 @@ body: |
%2:fpr32 = COPY $s2
%1:fpr32 = COPY $s1
%0:fpr32 = COPY $s0
- %4:fpr32 = nsz FADDSrr %0, %1, implicit $fpcr
- %5:fpr32 = nnan FADDSrr killed %4, %2, implicit $fpcr
- %6:fpr32 = ninf FADDSrr killed %5, %3, implicit $fpcr
+ %4:fpr32 = nsz nnan ninf FADDSrr %0, %1, implicit $fpcr
+ %5:fpr32 = nsz nnan FADDSrr killed %4, %2, implicit $fpcr
+ %6:fpr32 = nsz ninf FADDSrr killed %5, %3, implicit $fpcr
$s0 = COPY %6
RET_ReallyLR implicit $s0
diff --git a/llvm/test/CodeGen/AArch64/pr72777.ll b/llvm/test/CodeGen/AArch64/pr72777.ll
new file mode 100644
index 000000000000000..e9021d605f1fe4a
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/pr72777.ll
@@ -0,0 +1,24 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
+
+define i64 @f(i64 %0, i64 %1) {
+; CHECK-LABEL: f:
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr x9, x1, #0x1
+; CHECK-NEXT: add x10, x0, x0
+; CHECK-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000
+; CHECK-NEXT: add x9, x9, x10
+; CHECK-NEXT: lsl x10, x9, #1
+; CHECK-NEXT: cmp x9, #0
+; CHECK-NEXT: cinv x8, x8, ge
+; CHECK-NEXT: cmp x9, x10, asr #1
+; CHECK-NEXT: csel x0, x8, x10, ne
+; CHECK-NEXT: ret
+ %3 = or i64 1, %1
+ %4 = add i64 %3, %0
+ %5 = add nsw i64 %4, %0
+ %6 = call i64 @llvm.sshl.sat.i64(i64 %5, i64 1)
+ ret i64 %6
+}
+
+declare i64 @llvm.sshl.sat.i64(i64, i64)
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