[llvm] [lld] [XCOFF] Display branch-absolute targets in hex. (PR #72532)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 22 13:40:23 PST 2023
https://github.com/stephenpeckham updated https://github.com/llvm/llvm-project/pull/72532
>From eefa464df5d92b34d46336665b13f450743047d1 Mon Sep 17 00:00:00 2001
From: Stephen Peckham <speckham at us.ibm.com>
Date: Thu, 16 Nov 2023 11:46:28 -0500
Subject: [PATCH 1/4] Display branch-absolute targets in hex.
---
.../PowerPC/MCTargetDesc/PPCInstPrinter.cpp | 5 ++-
llvm/lib/Target/PowerPC/PPCRegisterInfo.td | 3 ++
.../tools/llvm-objdump/XCOFF/Inputs/abs32.o | Bin 0 -> 262 bytes
.../tools/llvm-objdump/XCOFF/Inputs/abs64.o | Bin 0 -> 319 bytes
.../llvm-objdump/XCOFF/disassemble-abs.test | 37 ++++++++++++++++++
5 files changed, 44 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/tools/llvm-objdump/XCOFF/Inputs/abs32.o
create mode 100644 llvm/test/tools/llvm-objdump/XCOFF/Inputs/abs64.o
create mode 100644 llvm/test/tools/llvm-objdump/XCOFF/disassemble-abs.test
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
index ccbb650c65365b4..f0a5cfcd5a78878 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
@@ -484,7 +484,10 @@ void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo,
if (!MI->getOperand(OpNo).isImm())
return printOperand(MI, OpNo, STI, O);
- O << SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
+ uint64_t Imm = MI->getOperand(OpNo).getImm() << 2;
+ if (!TT.isPPC64())
+ Imm &= 0xffffffff;
+ O << formatHex(Imm);
}
void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
index 6151faf403aaaf1..375e63654db1184 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -798,6 +798,7 @@ def directbrtarget : Operand<OtherVT> {
def absdirectbrtarget : Operand<OtherVT> {
let PrintMethod = "printAbsBranchOperand";
let EncoderMethod = "getAbsDirectBrEncoding";
+ let DecoderMethod = "decodeDirectBrTarget";
let ParserMatchClass = PPCDirectBrAsmOperand;
}
def PPCCondBrAsmOperand : AsmOperandClass {
@@ -814,6 +815,7 @@ def condbrtarget : Operand<OtherVT> {
def abscondbrtarget : Operand<OtherVT> {
let PrintMethod = "printAbsBranchOperand";
let EncoderMethod = "getAbsCondBrEncoding";
+ let DecoderMethod = "decodeCondBrTarget";
let ParserMatchClass = PPCCondBrAsmOperand;
}
def calltarget : Operand<iPTR> {
@@ -826,6 +828,7 @@ def calltarget : Operand<iPTR> {
def abscalltarget : Operand<iPTR> {
let PrintMethod = "printAbsBranchOperand";
let EncoderMethod = "getAbsDirectBrEncoding";
+ let DecoderMethod = "decodeDirectBrTarget";
let ParserMatchClass = PPCDirectBrAsmOperand;
}
def PPCCRBitMaskOperand : AsmOperandClass {
diff --git a/llvm/test/tools/llvm-objdump/XCOFF/Inputs/abs32.o b/llvm/test/tools/llvm-objdump/XCOFF/Inputs/abs32.o
new file mode 100644
index 0000000000000000000000000000000000000000..eda8e461736e033d4d2d7bc2b75a68ed4b8afdd4
GIT binary patch
literal 262
zcmZR)&%l@(X4=QVz>opN96-#VSCU#$0%9P51dwS1#35iICNQbs!N9=m*ucQ-!60Pj
z{r~?X#|C9D$A<q9Sq28CnIK(kK+M!Hp_i7KlM2?x!0`Vc4|6(WVp6eQF;oPFVuA6P
y7-1|NG*CVpqy}UU5C}pj2EE+G%seQY0VoeP2Wl$JaX at K4y|mK2<dV$%JO%*qP#WF<
literal 0
HcmV?d00001
diff --git a/llvm/test/tools/llvm-objdump/XCOFF/Inputs/abs64.o b/llvm/test/tools/llvm-objdump/XCOFF/Inputs/abs64.o
new file mode 100644
index 0000000000000000000000000000000000000000..ae9e0e87d001730a70e869ba95a71ca67db3ed1b
GIT binary patch
literal 319
zcmZSl&cK)&W*Wr+0aKtfhh9l)MG2IHg_3}ZB|zy4BsEM>wgQOuU|?W&Y+zvaU=T9%
z{{R1xV}r7nW5a)#8jupEnK0AXK)ik!4<yI({~r%iI%8r|v0gEV4+DQ-3?R(~Vly!!
zi9ndYkwioofb!WOHBi$9G1Z8I)PT)lfk;9f2{K1oFD)}Cl|e79G%vX%Ge3`kK`%Ek
HGmilPi{Kw(
literal 0
HcmV?d00001
diff --git a/llvm/test/tools/llvm-objdump/XCOFF/disassemble-abs.test b/llvm/test/tools/llvm-objdump/XCOFF/disassemble-abs.test
new file mode 100644
index 000000000000000..dc83b3540ca0a76
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/XCOFF/disassemble-abs.test
@@ -0,0 +1,37 @@
+# RUN: llvm-objdump -d %p/Inputs/abs32.o | \
+# RUN: FileCheck %s
+
+# RUN: llvm-objdump -d %p/Inputs/abs64.o | \
+# RUN: FileCheck --check-prefixes=CHECK64 %s
+
+## Object files assembled on AIX from the following source:
+## .csect [PR]
+##.main:
+## .globl .main
+## .extern .function
+## bla .function
+## btla .function
+## ba 0x1234
+## ba -32
+## bta 0x2348
+## bta -256
+
+CHECK: Inputs/abs32.o: file format aixcoff-rs6000
+CHECK: Disassembly of section .text:
+CHECK: 00000000 <.main>:
+CHECK: 0: 48 00 00 03 bla 0x0
+CHECK-NEXT: 4: 41 80 00 03 btla 0, 0x0
+CHECK-NEXT: 8: 48 00 12 36 ba 0x1234
+CHECK-NEXT: c: 4b ff ff e2 ba 0xffffffe0
+CHECK-NEXT: 10: 41 80 23 4a bta 0, 0x2348
+CHECK-NEXT: 14: 41 80 ff 02 bta 0, 0xffffff00
+
+CHECK64: Inputs/abs64.o: file format aix5coff64-rs6000
+CHECK64: Disassembly of section .text:
+CHECK64: 0000000000000000 <.main>:
+CHECK64-NEXT: 0: 48 00 00 03 bla 0x0
+CHECK64-NEXT: 4: 41 80 00 03 btla 0, 0x0
+CHECK64-NEXT: 8: 48 00 12 36 ba 0x1234
+CHECK64-NEXT: c: 4b ff ff e2 ba 0xffffffffffffffe0
+CHECK64-NEXT: 10: 41 80 23 4a bta 0, 0x2348
+CHECK64-NEXT: 14: 41 80 ff 02 bta 0, 0xffffffffffffff00
>From 0af851399a0accf49d33e2085af9e43ed21b999d Mon Sep 17 00:00:00 2001
From: Stephen Peckham <speckham at us.ibm.com>
Date: Wed, 22 Nov 2023 14:50:23 -0500
Subject: [PATCH 2/4] Fix ELF testcase
---
lld/test/ELF/ppc32-reloc-addr.s | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lld/test/ELF/ppc32-reloc-addr.s b/lld/test/ELF/ppc32-reloc-addr.s
index 78865b82ccbf1d4..9b40bce77aec485 100644
--- a/lld/test/ELF/ppc32-reloc-addr.s
+++ b/lld/test/ELF/ppc32-reloc-addr.s
@@ -22,7 +22,7 @@
.section .R_PPC_ADDR24,"ax", at progbits
ba a
# CHECK-LABEL: section .R_PPC_ADDR24:
-# CHECK: ba 4660
+# CHECK: ba 0x1234
.section .R_PPC_ADDR32,"a", at progbits
.long a
>From 93096eb1f3658b2cb91e00ff52d64b871f8cca3c Mon Sep 17 00:00:00 2001
From: Stephen Peckham <speckham at us.ibm.com>
Date: Wed, 22 Nov 2023 16:26:09 -0500
Subject: [PATCH 3/4] Fix additional ELF tests
---
llvm/test/MC/Disassembler/PowerPC/ppc64-operands.txt | 4 ++--
llvm/test/MC/PowerPC/ppc32-ba.s | 2 +-
llvm/test/MC/PowerPC/ppc64-operands.s | 8 ++++----
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-operands.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-operands.txt
index 3fcba735584b931..ad797a1818e7366 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64-operands.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-operands.txt
@@ -81,7 +81,7 @@
# CHECK: b .+1024
0x48 0x00 0x04 0x00
-# CHECK: ba 1024
+# CHECK: ba 0x400
0x48 0x00 0x04 0x02
# FIXME: decode as beq 0, .+1024
@@ -89,6 +89,6 @@
0x41 0x82 0x04 0x00
# FIXME: decode as beqa 0, 1024
-# CHECK: bta 2, 1024
+# CHECK: bta 2, 0x400
0x41 0x82 0x04 0x02
diff --git a/llvm/test/MC/PowerPC/ppc32-ba.s b/llvm/test/MC/PowerPC/ppc32-ba.s
index 133423b4e8c3123..a00de117800989b 100644
--- a/llvm/test/MC/PowerPC/ppc32-ba.s
+++ b/llvm/test/MC/PowerPC/ppc32-ba.s
@@ -2,5 +2,5 @@
# Check that large immediates in 32bit mode are accepted.
-# CHECK: ba -33554432 # encoding: [0x4a,0x00,0x00,0x02]
+# CHECK: ba 0xfe000000# encoding: [0x4a,0x00,0x00,0x02]
ba 0xfe000000
diff --git a/llvm/test/MC/PowerPC/ppc64-operands.s b/llvm/test/MC/PowerPC/ppc64-operands.s
index 9cd94bea6f815c1..366e1faf31357c5 100644
--- a/llvm/test/MC/PowerPC/ppc64-operands.s
+++ b/llvm/test/MC/PowerPC/ppc64-operands.s
@@ -128,16 +128,16 @@
# CHECK-LE: b .+1024 # encoding: [0x00,0x04,0x00,0x48]
b 1024
-# CHECK-BE: ba 1024 # encoding: [0x48,0x00,0x04,0x02]
-# CHECK-LE: ba 1024 # encoding: [0x02,0x04,0x00,0x48]
+# CHECK-BE: ba 0x400 # encoding: [0x48,0x00,0x04,0x02]
+# CHECK-LE: ba 0x400 # encoding: [0x02,0x04,0x00,0x48]
ba 1024
# CHECK-BE: beq 0, .+1024 # encoding: [0x41,0x82,0x04,0x00]
# CHECK-LE: beq 0, .+1024 # encoding: [0x00,0x04,0x82,0x41]
beq 1024
-# CHECK-BE: beqa 0, 1024 # encoding: [0x41,0x82,0x04,0x02]
-# CHECK-LE: beqa 0, 1024 # encoding: [0x02,0x04,0x82,0x41]
+# CHECK-BE: beqa 0, 0x400 # encoding: [0x41,0x82,0x04,0x02]
+# CHECK-LE: beqa 0, 0x400 # encoding: [0x02,0x04,0x82,0x41]
beqa 1024
# CHECK-BE: # encoding: [0x42,0x9f,A,0bAAAAAA01]
>From 6fdbc8fcdc9d5b426537c0fd70702f7db19984b1 Mon Sep 17 00:00:00 2001
From: Stephen Peckham <speckham at us.ibm.com>
Date: Wed, 22 Nov 2023 16:39:42 -0500
Subject: [PATCH 4/4] Updated test
---
llvm/test/MC/PowerPC/ppc32-ba.s | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/MC/PowerPC/ppc32-ba.s b/llvm/test/MC/PowerPC/ppc32-ba.s
index a00de117800989b..c12c0be5ba76bc3 100644
--- a/llvm/test/MC/PowerPC/ppc32-ba.s
+++ b/llvm/test/MC/PowerPC/ppc32-ba.s
@@ -2,5 +2,5 @@
# Check that large immediates in 32bit mode are accepted.
-# CHECK: ba 0xfe000000# encoding: [0x4a,0x00,0x00,0x02]
+# CHECK: ba 0xe000000 # encoding: [0x4a,0x00,0x00,0x02]
ba 0xfe000000
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