[llvm] [AMDGPU] Fix CPol operands of MUBUF atomics. (PR #73118)

[Ivan Kosarev via llvm-commits]

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@@ -1080,6 +1079,8 @@ def CPol_0 : DefaultOperand<CPol, 0>;
 def CPol_GLC1 : DefaultOperand<CPol, 1>;
 def CPol_GLC : ValuePredicatedOperand<CPol, "Op.getImm() & CPol::GLC">;
 def CPol_NonGLC : ValuePredicatedOperand<CPol, "!(Op.getImm() & CPol::GLC)", 1>;
+def CPol_GLC_WithDefault : DefaultOperand<CPol_GLC, !shl(1, CPolBit.GLC)>;
+def CPol_NonGLC_WithDefault : DefaultOperand<CPol_NonGLC, 0>;
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kosarev wrote:

The `*_WithDefault` operands are `OperandWithDefaultOps`, which they need to be because the patterns specified for the atomic instructions provide no value for the CPol operands.

https://github.com/llvm/llvm-project/pull/73118