[llvm] [RISCV] Add macro fusions for Xiangshan (PR #72362)

[Craig Topper via llvm-commits]

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@@ -0,0 +1,102 @@
+//==----- RISCVMacroFusion.td - Macro Fusion Definitions -----*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+// ===---------------------------------------------------------------------===//
+// The following definitions describe the macro fusion predicators.
+
+class RISCVMacroFusion<list<Instruction> first,list<Instruction> second,
+                             list<MCInstPredicate> extraFirstPreds = [],
+                             list<MCInstPredicate> extraSecondPreds = []>
+  : SimpleFusion<CheckAll<!listconcat([CheckOpcode<first>], extraFirstPreds)>,
+                 CheckAll<!listconcat([CheckOpcode<second>], extraSecondPreds)>>;
+
+def LUIADDI: RISCVMacroFusion<[LUI], [ADDI, ADDIW]>;
+
+// clear upper 32 bits / get lower 32 bits: slli r1, r0, 32 + srli r1, r1, 32
+def ClearUpper32Bits : RISCVMacroFusion<[SLLI], [SRLI],
+                                        [CheckImmOperand<2, 32>],
+                                        [CheckImmOperand<2, 32>]>;
+
+// clear upper 48 bits / get lower 16 bits: slli r1, r0, 48 + srli r1, r1, 48
+def ClearUpper48Bits : RISCVMacroFusion<[SLLI], [SRLI],
+                                        [CheckImmOperand<2, 48>],
+                                        [CheckImmOperand<2, 48>]>;
+
+// clear upper 48 bits / get lower 16 bits: slliw r1, r0, 16 + srliw r1, r1, 16
+def GetLower16Bits : RISCVMacroFusion<[SLLIW], [SRLIW],
+                                      [CheckImmOperand<2, 16>],
+                                      [CheckImmOperand<2, 16>]>;
+
+// sign-extend a 16-bit number: slliw r1, r0, 16 + sraiw r1, r1, 16
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topperc wrote:

Does LLVM generate this pattern? I think think we always use slli 48 + srai 48. Is that something that needs to be changed in isel?

https://github.com/llvm/llvm-project/pull/72362