[llvm] [AArch64] merge index address with large offset into base address (PR #72187)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 21 22:23:17 PST 2023
vfdff wrote:
> It might be worth doing this as a (late) AArch64ISelLowering DAG combine so that the add gets shared between multiple load/store instructions.
* Yes, the current solution does not implement the reuse of add, eg:
```
define i64 @LdOffset_i64_multi_offset(ptr %a) {
; CHECK-LABEL: LdOffset_i64_multi_offset:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: add x8, x0, #2031, lsl #12 // =8318976
; CHECK-NEXT: add x9, x0, #2031, lsl #12 // =8318976
; CHECK-NEXT: add x8, x8, #960
; CHECK-NEXT: ldr x9, [x9, #960]
; CHECK-NEXT: ldr x8, [x8, #2056]
; CHECK-NEXT: add x0, x8, x9
; CHECK-NEXT: ret
entry:
%arrayidx = getelementptr inbounds i64, ptr %a, i64 1039992
%0 = load i64, ptr %arrayidx, align 8
%arrayidx1 = getelementptr inbounds i64, ptr %a, i64 1040249
%1 = load i64, ptr %arrayidx1, align 8
%add = add nsw i64 %1, %0
ret i64 %add
}
```
* In that case, I think it's reasonable to go back to my previous plan? (I'll add more test cases if it's right direction).
I don't prefer to `DAG combine` because it seems we need similar code to address `load` and `store` separately
https://github.com/llvm/llvm-project/commit/bff3b81d921a7c69fd8a50dcbf7cd44776c73d19
https://github.com/llvm/llvm-project/pull/72187
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