[llvm] [MachinePipeliner] Fix store-store dependences (#72508) (PR #72575)

[Yuta Mukai via llvm-commits]

ytmukai wrote:

I don't fully understand, but it appears that adding edges for loop carried dependencies must be done in `addLoopCarriedDependences`. Then, `isLoopCarriedDep` is used to determine if the added order dependence is loop carried.
For example, the following code has no dependency edges between stores, so fixing `isLoopCarriedDep` is not enough to solve the problem: https://godbolt.org/z/xMdYT9Tfj

```
  ; The second store must be executed before the first store in the next iteration.
  store double 1.000000e+00, ptr %10, align 8 ; a[i] = 1
  store double %x1, ptr %11, align 8          ; a[i+1] = i
```

`addLoopCarriedDependences` does not add store-store dependency edges:

```
SU(5):   STD %16:g8rc, 8, %2:g8rc_and_g8rc_nox0 :: (store (s64) into %ir.10)
  # preds left       : 1
  # succs left       : 0
  # rdefs left       : 0
  Latency            : 1
  Depth              : 0
  Height             : 0
  Predecessors:
    SU(1): Data Latency=0 Reg=%2
SU(6):   DFSTOREf64 %14:vsfrc, 16, %2:g8rc_and_g8rc_nox0 :: (store (s64) into %ir.11)
  # preds left       : 2
  # succs left       : 0
  # rdefs left       : 0
  Latency            : 1
  Depth              : 9
  Height             : 0
  Predecessors:
    SU(4): Data Latency=7 Reg=%14
    SU(1): Data Latency=0 Reg=%2
```

The second store is scheduled illegally after the first store in the next iteration:

```
Inst (6)   DFSTOREf64 %14:vsfrc, 16, %2:g8rc_and_g8rc_nox0 :: (store (s64) into %ir.11)

	es:        9 ls: 7fffffff me: 7fffffff ms: 80000000
Trying to insert node between 9 and 11 II: 3
	insert at cycle 9   DFSTOREf64 %14:vsfrc, 16, %2:g8rc_and_g8rc_nox0 :: (store (s64) into %ir.11)

Inst (5)   STD %16:g8rc, 8, %2:g8rc_and_g8rc_nox0 :: (store (s64) into %ir.10)

	es:        0 ls: 7fffffff me: 7fffffff ms: 80000000
Trying to insert node between 0 and 2 II: 3
	failed to insert at cycle 0   STD %16:g8rc, 8, %2:g8rc_and_g8rc_nox0 :: (store (s64) into %ir.10)
	insert at cycle 1   STD %16:g8rc, 8, %2:g8rc_and_g8rc_nox0 :: (store (s64) into %ir.10)
```

https://github.com/llvm/llvm-project/pull/72575