[llvm] [AArch64] Allow LDR merge with same destination register by renaming (PR #71908)

[David Green via llvm-commits]

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@@ -546,3 +545,158 @@ body:             |
     RET undef $lr
 
 ...
+
+# During ISel, the order of load/store pairs can be optimized and changed
+# so that only a single register is used. Due to this register reuse, LDP/STPs
+# are not generated. These tests check that LDP/STPs will be generated after
+# register renaming is attempted.
+... 
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davemgreen wrote:

Remove these ...'s?

https://github.com/llvm/llvm-project/pull/71908