[llvm] b072ec5 - [AMDGPU] NFC. Run auto-update on a few tests
Joe Nash via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 21 10:53:49 PST 2023
Author: Joe Nash
Date: 2023-11-21T13:52:02-05:00
New Revision: b072ec5ec670b1de356efa23ebfb3165389e81b9
URL: https://github.com/llvm/llvm-project/commit/b072ec5ec670b1de356efa23ebfb3165389e81b9
DIFF: https://github.com/llvm/llvm-project/commit/b072ec5ec670b1de356efa23ebfb3165389e81b9.diff
LOG: [AMDGPU] NFC. Run auto-update on a few tests
Added:
Modified:
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll
llvm/test/CodeGen/AMDGPU/dual-source-blend-export.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll
index d7cbb5ec0dfef59..c8165c40ef8e7b3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll
@@ -14,7 +14,7 @@ define amdgpu_ps void @v_interp_f32(float inreg %i, float inreg %j, i32 inreg %m
; GCN-NEXT: v_mov_b32_e32 v4, s1
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GCN-NEXT: v_interp_p10_f32 v3, v0, v2, v0 wait_exp:1
-; GCN-NEXT: v_interp_p10_f32 v2, v1, v2, v1
+; GCN-NEXT: v_interp_p10_f32 v2, v1, v2, v1 wait_exp:0
; GCN-NEXT: v_interp_p2_f32 v5, v0, v4, v3 wait_exp:7
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GCN-NEXT: v_interp_p2_f32 v4, v1, v4, v5 wait_exp:7
@@ -47,7 +47,7 @@ define amdgpu_ps void @v_interp_f32_many(float inreg %i, float inreg %j, i32 inr
; GCN-NEXT: v_interp_p10_f32 v6, v0, v4, v0 wait_exp:3
; GCN-NEXT: v_interp_p10_f32 v7, v1, v4, v1 wait_exp:2
; GCN-NEXT: v_interp_p10_f32 v8, v2, v4, v2 wait_exp:1
-; GCN-NEXT: v_interp_p10_f32 v4, v3, v4, v3
+; GCN-NEXT: v_interp_p10_f32 v4, v3, v4, v3 wait_exp:0
; GCN-NEXT: v_interp_p2_f32 v6, v0, v5, v6 wait_exp:7
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GCN-NEXT: v_interp_p2_f32 v7, v1, v5, v7 wait_exp:7
@@ -89,7 +89,7 @@ define amdgpu_ps void @v_interp_f32_many_vm(ptr addrspace(1) %ptr, i32 inreg %m0
; GCN-NEXT: v_interp_p10_f32 v6, v2, v0, v2 wait_exp:3
; GCN-NEXT: v_interp_p10_f32 v7, v3, v0, v3 wait_exp:2
; GCN-NEXT: v_interp_p10_f32 v8, v4, v0, v4 wait_exp:1
-; GCN-NEXT: v_interp_p10_f32 v0, v5, v0, v5
+; GCN-NEXT: v_interp_p10_f32 v0, v5, v0, v5 wait_exp:0
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GCN-NEXT: v_interp_p2_f32 v6, v2, v1, v6 wait_exp:7
; GCN-NEXT: v_interp_p2_f32 v7, v3, v1, v7 wait_exp:7
@@ -130,7 +130,7 @@ define amdgpu_ps half @v_interp_f16(float inreg %i, float inreg %j, i32 inreg %m
; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v2, s1
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GCN-NEXT: v_interp_p10_f16_f32 v3, v1, v0, v1
+; GCN-NEXT: v_interp_p10_f16_f32 v3, v1, v0, v1 wait_exp:0
; GCN-NEXT: v_interp_p10_f16_f32 v0, v1, v0, v1 op_sel:[1,0,1,0] wait_exp:7
; GCN-NEXT: v_interp_p2_f16_f32 v3, v1, v2, v3 wait_exp:7
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
diff --git a/llvm/test/CodeGen/AMDGPU/dual-source-blend-export.ll b/llvm/test/CodeGen/AMDGPU/dual-source-blend-export.ll
index 545a894b45f7bfa..e8aa26c4f9a8dfb 100644
--- a/llvm/test/CodeGen/AMDGPU/dual-source-blend-export.ll
+++ b/llvm/test/CodeGen/AMDGPU/dual-source-blend-export.ll
@@ -18,7 +18,7 @@ define amdgpu_ps void @_amdgpu_ps_main(i32 inreg %PrimMask, <2 x float> %InterpC
; GCN-NEXT: v_mbcnt_hi_u32_b32 v8, -1, v8
; GCN-NEXT: v_interp_p10_f32 v9, v5, v3, v5 wait_exp:2
; GCN-NEXT: v_interp_p10_f32 v11, v6, v3, v6 wait_exp:1
-; GCN-NEXT: v_interp_p10_f32 v10, v7, v3, v7
+; GCN-NEXT: v_interp_p10_f32 v10, v7, v3, v7 wait_exp:0
; GCN-NEXT: v_interp_p10_f32 v3, v4, v3, v4 wait_exp:7
; GCN-NEXT: v_interp_p2_f32 v5, v5, v2, v9 wait_exp:7
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
index c643d1c776cbef2..0113d8a82103bb4 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
@@ -14,7 +14,7 @@ define amdgpu_ps void @v_interp_f32(float inreg %i, float inreg %j, i32 inreg %m
; GCN-NEXT: v_mov_b32_e32 v4, s1
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GCN-NEXT: v_interp_p10_f32 v3, v0, v2, v0 wait_exp:1
-; GCN-NEXT: v_interp_p10_f32 v2, v1, v2, v1
+; GCN-NEXT: v_interp_p10_f32 v2, v1, v2, v1 wait_exp:0
; GCN-NEXT: v_interp_p2_f32 v5, v0, v4, v3 wait_exp:7
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GCN-NEXT: v_interp_p2_f32 v4, v1, v4, v5 wait_exp:7
@@ -47,7 +47,7 @@ define amdgpu_ps void @v_interp_f32_many(float inreg %i, float inreg %j, i32 inr
; GCN-NEXT: v_interp_p10_f32 v6, v0, v4, v0 wait_exp:3
; GCN-NEXT: v_interp_p10_f32 v7, v1, v4, v1 wait_exp:2
; GCN-NEXT: v_interp_p10_f32 v8, v2, v4, v2 wait_exp:1
-; GCN-NEXT: v_interp_p10_f32 v4, v3, v4, v3
+; GCN-NEXT: v_interp_p10_f32 v4, v3, v4, v3 wait_exp:0
; GCN-NEXT: v_interp_p2_f32 v6, v0, v5, v6 wait_exp:7
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GCN-NEXT: v_interp_p2_f32 v7, v1, v5, v7 wait_exp:7
@@ -89,7 +89,7 @@ define amdgpu_ps void @v_interp_f32_many_vm(ptr addrspace(1) %ptr, i32 inreg %m0
; GCN-NEXT: v_interp_p10_f32 v6, v2, v0, v2 wait_exp:3
; GCN-NEXT: v_interp_p10_f32 v7, v3, v0, v3 wait_exp:2
; GCN-NEXT: v_interp_p10_f32 v8, v4, v0, v4 wait_exp:1
-; GCN-NEXT: v_interp_p10_f32 v0, v5, v0, v5
+; GCN-NEXT: v_interp_p10_f32 v0, v5, v0, v5 wait_exp:0
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GCN-NEXT: v_interp_p2_f32 v6, v2, v1, v6 wait_exp:7
; GCN-NEXT: v_interp_p2_f32 v7, v3, v1, v7 wait_exp:7
@@ -130,7 +130,7 @@ define amdgpu_ps half @v_interp_f16(float inreg %i, float inreg %j, i32 inreg %m
; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v2, s1
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GCN-NEXT: v_interp_p10_f16_f32 v3, v1, v0, v1
+; GCN-NEXT: v_interp_p10_f16_f32 v3, v1, v0, v1 wait_exp:0
; GCN-NEXT: v_interp_p10_f16_f32 v0, v1, v0, v1 op_sel:[1,0,1,0] wait_exp:7
; GCN-NEXT: v_interp_p2_f16_f32 v3, v1, v2, v3 wait_exp:7
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
diff --git a/llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll b/llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll
index 3020991e8a930c1..e29f09dcac0248a 100644
--- a/llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll
+++ b/llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll
@@ -9,7 +9,8 @@
define hidden void @ptr_arg_split_subregs(ptr %arg1) #0 !dbg !9 {
; CHECK-LABEL: ptr_arg_split_subregs:
; CHECK: .Lfunc_begin0:
-; CHECK: .loc 1 5 0 ; example.cpp:5:0
+; CHECK-NEXT: .file 1 "temp" "example.cpp"
+; CHECK-NEXT: .loc 1 5 0 ; example.cpp:5:0
; CHECK-NEXT: .cfi_sections .debug_frame
; CHECK-NEXT: .cfi_startproc
; CHECK-NEXT: ; %bb.0:
@@ -24,7 +25,6 @@ define hidden void @ptr_arg_split_subregs(ptr %arg1) #0 !dbg !9 {
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_setpc_b64 s[30:31]
; CHECK-NEXT: .Ltmp1:
-; CHECK: .cfi_endproc
call void @llvm.dbg.declare(metadata ptr %arg1, metadata !20, metadata !DIExpression()), !dbg !21
%gep1 = getelementptr inbounds %struct.A, ptr %arg1, i32 0, i32 0, i32 99, !dbg !22
store i32 1, ptr %gep1, align 4, !dbg !23
@@ -45,7 +45,7 @@ define hidden void @ptr_arg_split_reg_mem(<30 x i32>, ptr %arg2) #0 !dbg !25 {
; CHECK-NEXT: ; %bb.0:
; CHECK-NEXT: ;DEBUG_VALUE: ptr_arg_split_reg_mem:b <- [$vgpr30+0]
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32{{$}}
+; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32
; CHECK-NEXT: v_mov_b32_e32 v0, 1
; CHECK-NEXT: .Ltmp2:
; CHECK-NEXT: .loc 1 12 13 prologue_end ; example.cpp:12:13
@@ -55,7 +55,6 @@ define hidden void @ptr_arg_split_reg_mem(<30 x i32>, ptr %arg2) #0 !dbg !25 {
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_setpc_b64 s[30:31]
; CHECK-NEXT: .Ltmp3:
-; CHECK: .cfi_endproc
call void @llvm.dbg.declare(metadata ptr %arg2, metadata !26, metadata !DIExpression()), !dbg !27
%gep2 = getelementptr inbounds %struct.A, ptr %arg2, i32 0, i32 0, i32 99, !dbg !28
store i32 1, ptr %gep2, align 4, !dbg !29
@@ -82,7 +81,6 @@ define hidden void @ptr_arg_in_memory(<32 x i32>, ptr %arg3) #0 !dbg !31 {
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_setpc_b64 s[30:31]
; CHECK-NEXT: .Ltmp5:
-; CHECK: .cfi_endproc
call void @llvm.dbg.declare(metadata ptr %arg3, metadata !32, metadata !DIExpression()), !dbg !33
%gep3 = getelementptr inbounds %struct.A, ptr %arg3, i32 0, i32 0, i32 99, !dbg !34
store i32 1, ptr %gep3, align 4, !dbg !35
More information about the llvm-commits
mailing list