[llvm] [bolt] Support arm64 FP register spills (PR #73021)

[via llvm-commits]

https://github.com/eleviant created https://github.com/llvm/llvm-project/pull/73021

At the moment llvm-bolt fails when analyzing jump tables on aarch64 in case FP register spill/reload is used.

>From 4f9076e7f1e7ecee71561979513eecf5b7f51324 Mon Sep 17 00:00:00 2001
From: Evgeny Leviant <eleviant at accesssoftek.com>
Date: Tue, 21 Nov 2023 20:35:56 +0300
Subject: [PATCH] [bolt] Support arm64 FP register spills

At the moment llvm-bolt fails when analyzing jump tables on aarch64
in case FP register spill/reload is used.
---
 .../Target/AArch64/AArch64MCPlusBuilder.cpp   |  5 ++
 bolt/test/AArch64/fp-reg-spill.test           | 52 +++++++++++++++++++
 2 files changed, 57 insertions(+)
 create mode 100644 bolt/test/AArch64/fp-reg-spill.test

diff --git a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
index b852b9fbc9c52f4..68a6e7aa191fc7f 100644
--- a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
+++ b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
@@ -314,6 +314,11 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
 
   bool isRegToRegMove(const MCInst &Inst, MCPhysReg &From,
                       MCPhysReg &To) const override {
+    if (Inst.getOpcode() == AArch64::FMOVDXr) {
+      From = Inst.getOperand(1).getReg();
+      To = Inst.getOperand(0).getReg();
+      return true;
+    }
     if (Inst.getOpcode() != AArch64::ORRXrs)
       return false;
     if (Inst.getOperand(1).getReg() != AArch64::XZR)
diff --git a/bolt/test/AArch64/fp-reg-spill.test b/bolt/test/AArch64/fp-reg-spill.test
new file mode 100644
index 000000000000000..ebd19c790ebb170
--- /dev/null
+++ b/bolt/test/AArch64/fp-reg-spill.test
@@ -0,0 +1,52 @@
+# REQUIRES: system-linux
+# RUN: yaml2obj %s -o %t.elf
+# RUN: llvm-bolt --jump-tables=move %t.elf -o %t.bolt
+
+--- !ELF
+FileHeader:
+  Class:   ELFCLASS64
+  Data:    ELFDATA2LSB
+  Type:    ET_EXEC
+  Machine: EM_AARCH64
+  Entry:   0x100004
+Sections:
+  - Type:         SHT_PROGBITS
+    Name:         .text
+    Flags:        [ SHF_ALLOC, SHF_EXECINSTR ]
+    AddressAlign: 8
+    Offset:       0x1000
+    Address:      0x100000
+# _foo:
+#   ret
+# _start:
+#   adr	x6, #0
+#   fmov	d18, x6
+#   fmov	x5, d18
+#   ldrb	w5, [x5, w1, uxtw]
+#   add	x5, x6, w5, sxtb #2
+#   br	x5
+    Content:      "c0035fd606000010d200679e4502669ea5486138c588258ba0001fd6"
+  - Type:         SHT_RELA
+    Name:         .rela.text
+    Relocations:
+      - Offset:          0x4
+        Symbol:          _foo
+        Type:            R_AARCH64_ADR_PREL_LO21
+Symbols:
+  - Name:    _foo
+    Section: .text
+    Value:   0x100000
+    Binding: STB_GLOBAL
+    Type:    STT_FUNC
+  - Name:    _start
+    Section: .text
+    Value:   0x100004
+    Binding: STB_GLOBAL
+    Type:    STT_FUNC
+ProgramHeaders:
+  - Type:         PT_LOAD
+    FileSize:     0x18
+    MemSize:      0x18
+    VAddr:        0x100000
+    PAddr:        0x100000
+    Offset:       0x1000