[llvm] a1652fd - [InstCombine] Add tests for incorrect shift nneg inference (NFC)

[Nikita Popov via llvm-commits]

Author: Nikita Popov
Date: 2023-11-21T15:47:55+01:00
New Revision: a1652fdb5ebf4a7d94d28200765232ebc2ba7c62

URL: https://github.com/llvm/llvm-project/commit/a1652fdb5ebf4a7d94d28200765232ebc2ba7c62
DIFF: https://github.com/llvm/llvm-project/commit/a1652fdb5ebf4a7d94d28200765232ebc2ba7c62.diff

LOG: [InstCombine] Add tests for incorrect shift nneg inference (NFC)

The second test is a miscompile.

Added: 
    

Modified: 
    llvm/test/Transforms/InstCombine/shift.ll

Removed: 
    


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diff  --git a/llvm/test/Transforms/InstCombine/shift.ll b/llvm/test/Transforms/InstCombine/shift.ll
index 8c785c3734cfb99..1cb1ac327291622 100644
--- a/llvm/test/Transforms/InstCombine/shift.ll
+++ b/llvm/test/Transforms/InstCombine/shift.ll
@@ -2195,4 +2195,26 @@ define i16 @ashr_umax_demanded(i16 %x) {
   ret i16 %shr
 }
 
+define i128 @shift_zext_nneg(i8 %arg) {
+; CHECK-LABEL: @shift_zext_nneg(
+; CHECK-NEXT:    [[EXT:%.*]] = zext nneg i8 [[ARG:%.*]] to i128
+; CHECK-NEXT:    [[SHL:%.*]] = shl nuw i128 1, [[EXT]]
+; CHECK-NEXT:    ret i128 [[SHL]]
+;
+  %ext = zext i8 %arg to i128
+  %shl = shl i128 1, %ext
+  ret i128 %shl
+}
+
+define i129 @shift_zext_not_nneg(i8 %arg) {
+; CHECK-LABEL: @shift_zext_not_nneg(
+; CHECK-NEXT:    [[EXT:%.*]] = zext nneg i8 [[ARG:%.*]] to i129
+; CHECK-NEXT:    [[SHL:%.*]] = shl nuw nsw i129 1, [[EXT]]
+; CHECK-NEXT:    ret i129 [[SHL]]
+;
+  %ext = zext i8 %arg to i129
+  %shl = shl i129 1, %ext
+  ret i129 %shl
+}
+
 declare i16 @llvm.umax.i16(i16, i16)