[llvm] [TableGen] Add a backend to generate MacroFusion predicators (PR #72222)
Wang Pengcheng via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 21 00:13:49 PST 2023
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/72222
>From 087f84e37880283954f61f75b8ae23b42978bd7c Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Fri, 10 Nov 2023 18:18:18 +0800
Subject: [PATCH] [TableGen] Add a backend to generate MacroFusion predicators
`FusionPredicate` is used to predicate if target instruction matches
the requirement. The targets can be firstMI, secondMI or both.
The `Fusion` contains a list of `FusionPredicate`. The generated code
will be like:
```
bool isNAME(const TargetInstrInfo &TII,
const TargetSubtargetInfo &STI,
const MachineInstr *FirstMI,
const MachineInstr &SecondMI) {
auto &MRI = SecondMI.getMF()->getRegInfo();
/* Predicates */
return true;
}
```
A boilerplate class called `SimpleFusion` is added. `SimpleFusion` has
a predefined structure of predicates and accepts predicate for
`firstMI`, predicate for `secondMI` and epilog/prolog as arguments.
The generated code for `SimpleFusion` will be like:
```
bool isNAME(const TargetInstrInfo &TII,
const TargetSubtargetInfo &STI,
const MachineInstr *FirstMI,
const MachineInstr &SecondMI) {
auto &MRI = SecondMI.getMF()->getRegInfo();
/* Prolog */
/* Predicate for `SecondMI` */
/* Wildcard */
/* Predicate for `FirstMI` */
/* Check One Use */
/* Tie registers */
/* Epilog */
return true;
```
---
.../llvm/Target/TargetInstrPredicate.td | 6 +
llvm/include/llvm/Target/TargetSchedule.td | 113 ++++++++++
llvm/utils/TableGen/CMakeLists.txt | 1 +
.../TableGen/MacroFusionPredicatorEmitter.cpp | 203 ++++++++++++++++++
llvm/utils/TableGen/PredicateExpander.cpp | 8 +
llvm/utils/TableGen/PredicateExpander.h | 1 +
6 files changed, 332 insertions(+)
create mode 100644 llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp
diff --git a/llvm/include/llvm/Target/TargetInstrPredicate.td b/llvm/include/llvm/Target/TargetInstrPredicate.td
index 9f2cde9d923050a..82c4c7b23a49b6a 100644
--- a/llvm/include/llvm/Target/TargetInstrPredicate.td
+++ b/llvm/include/llvm/Target/TargetInstrPredicate.td
@@ -95,6 +95,12 @@ class MCOperandPredicate<int Index> : MCInstPredicate {
// Return true if machine operand at position `Index` is a register operand.
class CheckIsRegOperand<int Index> : MCOperandPredicate<Index>;
+// Return true if machine operand at position `Index` is a virtual register operand.
+class CheckIsVRegOperand<int Index> : MCOperandPredicate<Index>;
+
+// Return true if machine operand at position `Index` is not a virtual register operand.
+class CheckIsNotVRegOperand<int Index> : CheckNot<CheckIsVRegOperand<Index>>;
+
// Return true if machine operand at position `Index` is an immediate operand.
class CheckIsImmOperand<int Index> : MCOperandPredicate<Index>;
diff --git a/llvm/include/llvm/Target/TargetSchedule.td b/llvm/include/llvm/Target/TargetSchedule.td
index 949baa5d2105c45..74c9cd085b4ee2e 100644
--- a/llvm/include/llvm/Target/TargetSchedule.td
+++ b/llvm/include/llvm/Target/TargetSchedule.td
@@ -584,3 +584,116 @@ class MemoryQueue<ProcResourceKind PR> {
class LoadQueue<ProcResourceKind LDQueue> : MemoryQueue<LDQueue>;
class StoreQueue<ProcResourceKind STQueue> : MemoryQueue<STQueue>;
+
+// The target instruction that FusionPredicate will be evaluated on.
+class FusionTarget;
+def first : FusionTarget;
+def second : FusionTarget;
+def both : FusionTarget;
+
+// Base class of FusionPredicate, etc. The avaliable variables are:
+// * const TargetInstrInfo &TII
+// * const TargetSubtargetInfo &STI
+// * const MachineRegisterInfo &MRI
+// * const MachineInstr *FirstMI
+// * const MachineInstr &SecondMI
+class FusionPredicate<FusionTarget target> {
+ FusionTarget Target = target;
+}
+class FirstFusionPredicate: FusionPredicate<first>;
+class SecondFusionPredicate: FusionPredicate<second>;
+class BothFusionPredicate: FusionPredicate<both>;
+
+// FusionPredicate with raw code predicate.
+class FusionPredicateWithCode<code pred> : FusionPredicate<both> {
+ code Predicate = pred;
+}
+
+// FusionPredicate with MCInstPredicate.
+class FusionPredicateWithMCInstPredicate<FusionTarget target, MCInstPredicate pred>
+ : FusionPredicate<target> {
+ MCInstPredicate Predicate = pred;
+}
+class FirstFusionPredicateWithMCInstPredicate<MCInstPredicate pred>
+ : FusionPredicateWithMCInstPredicate<first, pred>;
+class SecondFusionPredicateWithMCInstPredicate<MCInstPredicate pred>
+ : FusionPredicateWithMCInstPredicate<second, pred>;
+// The pred will be applied on both firstMI and secondMI.
+class BothFusionPredicateWithMCInstPredicate<MCInstPredicate pred>
+ : FusionPredicateWithMCInstPredicate<second, pred>;
+
+// Tie firstOpIdx and secondOpIdx. The operand of `FirstMI` at position
+// `firstOpIdx` should be the same as the operand of `SecondMI` at position
+// `secondOpIdx`.
+class TieReg<int firstOpIdx, int secondOpIdx> : BothFusionPredicate {
+ int FirstOpIdx = firstOpIdx;
+ int SecondOpIdx = secondOpIdx;
+}
+
+// A predicate for wildcard. The generated code will be like:
+// ```
+// if (!FirstMI)
+// return ReturnValue;
+// ```
+class WildcardPred<bit ret> : FirstFusionPredicate {
+ bit ReturnValue = ret;
+}
+def WildcardFalse : WildcardPred<0>;
+def WildcardTrue : WildcardPred<1>;
+
+// Indicates that the destination register of `FirstMI` should have one use if
+// it is a virtual register.
+class OneUsePred : FirstFusionPredicate;
+def OneUse : OneUsePred;
+
+// Handled by MacroFusionPredicatorEmitter backend.
+// The generated predicator will be like:
+// ```
+// bool isNAME(const TargetInstrInfo &TII,
+// const TargetSubtargetInfo &STI,
+// const MachineInstr *FirstMI,
+// const MachineInstr &SecondMI) {
+// auto &MRI = SecondMI.getMF()->getRegInfo();
+// /* Predicates */
+// return true;
+// }
+// ```
+class Fusion<list<FusionPredicate> predicates> {
+ list<FusionPredicate> Predicates = predicates;
+}
+
+// The generated predicator will be like:
+// ```
+// bool isNAME(const TargetInstrInfo &TII,
+// const TargetSubtargetInfo &STI,
+// const MachineInstr *FirstMI,
+// const MachineInstr &SecondMI) {
+// auto &MRI = SecondMI.getMF()->getRegInfo();
+// /* Prolog */
+// /* Predicate for `SecondMI` */
+// /* Wildcard */
+// /* Predicate for `FirstMI` */
+// /* Check One Use */
+// /* Tie registers */
+// /* Epilog */
+// return true;
+// }
+// ```
+class SimpleFusion<MCInstPredicate firstPred, MCInstPredicate secondPred,
+ list<FusionPredicate> prolog = [],
+ list<FusionPredicate> epilog = []>
+ : Fusion<!listconcat(
+ prolog,
+ [
+ SecondFusionPredicateWithMCInstPredicate<secondPred>,
+ WildcardTrue,
+ FirstFusionPredicateWithMCInstPredicate<firstPred>,
+ SecondFusionPredicateWithMCInstPredicate<
+ CheckAny<[
+ CheckIsVRegOperand<0>,
+ CheckSameRegOperand<0, 1>
+ ]>>,
+ OneUse,
+ TieReg<0, 1>,
+ ],
+ epilog)>;
diff --git a/llvm/utils/TableGen/CMakeLists.txt b/llvm/utils/TableGen/CMakeLists.txt
index 071ea3bc07054bb..f765cc36d3bebed 100644
--- a/llvm/utils/TableGen/CMakeLists.txt
+++ b/llvm/utils/TableGen/CMakeLists.txt
@@ -72,6 +72,7 @@ add_tablegen(llvm-tblgen LLVM
PredicateExpander.cpp
PseudoLoweringEmitter.cpp
CompressInstEmitter.cpp
+ MacroFusionPredicatorEmitter.cpp
RegisterBankEmitter.cpp
RegisterInfoEmitter.cpp
SearchableTableEmitter.cpp
diff --git a/llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp b/llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp
new file mode 100644
index 000000000000000..b1cbbce6cea2eb8
--- /dev/null
+++ b/llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp
@@ -0,0 +1,203 @@
+//===------ MacroFusionPredicatorEmitter.cpp - Generator for Fusion ------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---------------------------------------------------------------------===//
+//
+// MacroFusionPredicatorEmitter implements a TableGen-driven predicators
+// generator for macro-op fusions.
+//
+//===---------------------------------------------------------------------===//
+
+#include "CodeGenTarget.h"
+#include "PredicateExpander.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/TableGen/Error.h"
+#include "llvm/TableGen/Record.h"
+#include "llvm/TableGen/TableGenBackend.h"
+#include <set>
+#include <vector>
+
+using namespace llvm;
+
+#define DEBUG_TYPE "macro-fusion-predicator"
+
+namespace {
+class MacroFusionPredicatorEmitter {
+ RecordKeeper &Records;
+ CodeGenTarget Target;
+
+ void emitMacroFusionDecl(std::vector<Record *> Fusions, PredicateExpander &PE,
+ raw_ostream &OS);
+ void emitMacroFusionImpl(std::vector<Record *> Fusions, PredicateExpander &PE,
+ raw_ostream &OS);
+ void emitPredicates(std::vector<Record *> &FirstPredicate,
+ PredicateExpander &PE, raw_ostream &OS);
+ void emitFirstPredicate(Record *SecondPredicate, PredicateExpander &PE,
+ raw_ostream &OS);
+ void emitSecondPredicate(Record *SecondPredicate, PredicateExpander &PE,
+ raw_ostream &OS);
+ void emitBothPredicate(Record *Predicates, PredicateExpander &PE,
+ raw_ostream &OS);
+
+public:
+ MacroFusionPredicatorEmitter(RecordKeeper &R) : Records(R), Target(R) {}
+
+ void run(raw_ostream &OS);
+};
+} // End anonymous namespace.
+
+void MacroFusionPredicatorEmitter::emitMacroFusionDecl(
+ std::vector<Record *> Fusions, PredicateExpander &PE, raw_ostream &OS) {
+ OS << "#ifdef GET_" << Target.getName() << "_MACRO_FUSION_PRED_DECL\n\n";
+
+ for (Record *Fusion : Fusions) {
+ OS << "bool is" << Fusion->getName() << "(const TargetInstrInfo &, "
+ << "const TargetSubtargetInfo &, " << "const MachineInstr *, "
+ << "const MachineInstr &);\n";
+ }
+
+ OS << "\n#endif\n";
+ OS << "#undef GET_" << Target.getName() << "_MACRO_FUSION_PRED_DECL\n";
+}
+
+void MacroFusionPredicatorEmitter::emitMacroFusionImpl(
+ std::vector<Record *> Fusions, PredicateExpander &PE, raw_ostream &OS) {
+ OS << "#ifdef GET_" << Target.getName() << "_MACRO_FUSION_PRED_IMPL\n\n";
+
+ for (Record *Fusion : Fusions) {
+ std::vector<Record *> Predicates =
+ Fusion->getValueAsListOfDefs("Predicates");
+
+ OS << "bool is" << Fusion->getName() << "(\n";
+ OS.indent(5) << "const TargetInstrInfo &TII,\n";
+ OS.indent(5) << "const TargetSubtargetInfo &STI,\n";
+ OS.indent(5) << "const MachineInstr *FirstMI,\n";
+ OS.indent(5) << "const MachineInstr &SecondMI) {\n";
+ OS.indent(2) << "auto &MRI = SecondMI.getMF()->getRegInfo();\n";
+
+ emitPredicates(Predicates, PE, OS);
+
+ OS.indent(2) << "return true;\n";
+ OS << "}\n";
+ }
+
+ OS << "\n#endif\n";
+ OS << "#undef GET_" << Target.getName() << "_MACRO_FUSION_PRED_IMPL\n\n";
+}
+
+void MacroFusionPredicatorEmitter::emitPredicates(
+ std::vector<Record *> &Predicates, PredicateExpander &PE, raw_ostream &OS) {
+ for (Record *Predicate : Predicates) {
+ Record *Target = Predicate->getValueAsDef("Target");
+ if (Target->getName() == "first")
+ emitFirstPredicate(Predicate, PE, OS);
+ else if (Target->getName() == "second")
+ emitSecondPredicate(Predicate, PE, OS);
+ else if (Target->getName() == "both")
+ emitBothPredicate(Predicate, PE, OS);
+ else
+ PrintFatalError(Target->getLoc(),
+ "Unsupported 'FusionTarget': " + Target->getName());
+ }
+}
+
+void MacroFusionPredicatorEmitter::emitFirstPredicate(Record *Predicate,
+ PredicateExpander &PE,
+ raw_ostream &OS) {
+ if (Predicate->isSubClassOf("WildcardPred")) {
+ OS.indent(2) << "if (!FirstMI)\n";
+ OS.indent(2) << " return "
+ << (Predicate->getValueAsBit("ReturnValue") ? "true" : "false")
+ << ";\n";
+ } else if (Predicate->isSubClassOf("OneUsePred")) {
+ OS.indent(2) << "{\n";
+ OS.indent(4) << "Register FirstDest = FirstMI->getOperand(0).getReg();\n";
+ OS.indent(4)
+ << "if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))\n";
+ OS.indent(4) << " return false;\n";
+ OS.indent(2) << "}\n";
+ } else if (Predicate->isSubClassOf(
+ "FirstFusionPredicateWithMCInstPredicate")) {
+ OS.indent(2) << "{\n";
+ OS.indent(4) << "const MachineInstr *MI = FirstMI;\n";
+ OS.indent(4) << "if (";
+ PE.setNegatePredicate(true);
+ PE.setIndentLevel(3);
+ PE.expandPredicate(OS, Predicate->getValueAsDef("Predicate"));
+ OS << ")\n";
+ OS.indent(4) << " return false;\n";
+ OS.indent(2) << "}\n";
+ } else {
+ PrintFatalError(Predicate->getLoc(),
+ "Unsupported predicate for first instruction: " +
+ Predicate->getType()->getAsString());
+ }
+}
+
+void MacroFusionPredicatorEmitter::emitSecondPredicate(Record *Predicate,
+ PredicateExpander &PE,
+ raw_ostream &OS) {
+ if (Predicate->isSubClassOf("SecondFusionPredicateWithMCInstPredicate")) {
+ OS.indent(2) << "{\n";
+ OS.indent(4) << "const MachineInstr *MI = &SecondMI;\n";
+ OS.indent(4) << "if (";
+ PE.setNegatePredicate(true);
+ PE.setIndentLevel(3);
+ PE.expandPredicate(OS, Predicate->getValueAsDef("Predicate"));
+ OS << ")\n";
+ OS.indent(4) << " return false;\n";
+ OS.indent(2) << "}\n";
+ } else {
+ PrintFatalError(Predicate->getLoc(),
+ "Unsupported predicate for first instruction: " +
+ Predicate->getType()->getAsString());
+ }
+}
+
+void MacroFusionPredicatorEmitter::emitBothPredicate(Record *Predicate,
+ PredicateExpander &PE,
+ raw_ostream &OS) {
+ if (Predicate->isSubClassOf("FusionPredicateWithCode"))
+ OS << Predicate->getValueAsString("Predicate");
+ else if (Predicate->isSubClassOf("BothFusionPredicateWithMCInstPredicate")) {
+ Record *MCPred = Predicate->getValueAsDef("Predicate");
+ emitFirstPredicate(MCPred, PE, OS);
+ emitSecondPredicate(MCPred, PE, OS);
+ } else if (Predicate->isSubClassOf("TieReg")) {
+ int FirstOpIdx = Predicate->getValueAsInt("FirstOpIdx");
+ int SecondOpIdx = Predicate->getValueAsInt("SecondOpIdx");
+ OS.indent(2) << "if (!(FirstMI->getOperand(" << FirstOpIdx
+ << ").isReg() &&\n";
+ OS.indent(2) << " SecondMI.getOperand(" << SecondOpIdx
+ << ").isReg() &&\n";
+ OS.indent(2) << " FirstMI->getOperand(" << FirstOpIdx
+ << ").getReg() == SecondMI.getOperand(" << SecondOpIdx
+ << ").getReg()))\n";
+ OS.indent(2) << " return false;\n";
+ } else
+ PrintFatalError(Predicate->getLoc(),
+ "Unsupported predicate for both instruction: " +
+ Predicate->getType()->getAsString());
+}
+
+void MacroFusionPredicatorEmitter::run(raw_ostream &OS) {
+ // Emit file header.
+ emitSourceFileHeader("Macro Fusion Predicators", OS);
+
+ PredicateExpander PE(Target.getName());
+ PE.setByRef(false);
+ PE.setExpandForMC(false);
+
+ std::vector<Record *> Fusions = Records.getAllDerivedDefinitions("Fusion");
+ // Sort macro fusions by name.
+ sort(Fusions, LessRecord());
+ emitMacroFusionDecl(Fusions, PE, OS);
+ emitMacroFusionImpl(Fusions, PE, OS);
+}
+
+static TableGen::Emitter::OptClass<MacroFusionPredicatorEmitter>
+ X("gen-macro-fusion-pred", "Generate macro fusion predicators.");
diff --git a/llvm/utils/TableGen/PredicateExpander.cpp b/llvm/utils/TableGen/PredicateExpander.cpp
index 8f96d3307ded8be..d3a73e02cd916f8 100644
--- a/llvm/utils/TableGen/PredicateExpander.cpp
+++ b/llvm/utils/TableGen/PredicateExpander.cpp
@@ -194,6 +194,11 @@ void PredicateExpander::expandCheckIsRegOperand(raw_ostream &OS, int OpIndex) {
<< "getOperand(" << OpIndex << ").isReg() ";
}
+void PredicateExpander::expandCheckIsVRegOperand(raw_ostream &OS, int OpIndex) {
+ OS << (shouldNegate() ? "!" : "") << "MI" << (isByRef() ? "." : "->")
+ << "getOperand(" << OpIndex << ").getReg().isVirtual()";
+}
+
void PredicateExpander::expandCheckIsImmOperand(raw_ostream &OS, int OpIndex) {
OS << (shouldNegate() ? "!" : "") << "MI" << (isByRef() ? "." : "->")
<< "getOperand(" << OpIndex << ").isImm() ";
@@ -319,6 +324,9 @@ void PredicateExpander::expandPredicate(raw_ostream &OS, const Record *Rec) {
if (Rec->isSubClassOf("CheckIsRegOperand"))
return expandCheckIsRegOperand(OS, Rec->getValueAsInt("OpIndex"));
+ if (Rec->isSubClassOf("CheckIsVRegOperand"))
+ return expandCheckIsVRegOperand(OS, Rec->getValueAsInt("OpIndex"));
+
if (Rec->isSubClassOf("CheckIsImmOperand"))
return expandCheckIsImmOperand(OS, Rec->getValueAsInt("OpIndex"));
diff --git a/llvm/utils/TableGen/PredicateExpander.h b/llvm/utils/TableGen/PredicateExpander.h
index 27f049a715aad56..cfb0a3d51e67764 100644
--- a/llvm/utils/TableGen/PredicateExpander.h
+++ b/llvm/utils/TableGen/PredicateExpander.h
@@ -75,6 +75,7 @@ class PredicateExpander {
bool IsCheckAll);
void expandTIIFunctionCall(raw_ostream &OS, StringRef MethodName);
void expandCheckIsRegOperand(raw_ostream &OS, int OpIndex);
+ void expandCheckIsVRegOperand(raw_ostream &OS, int OpIndex);
void expandCheckIsImmOperand(raw_ostream &OS, int OpIndex);
void expandCheckInvalidRegOperand(raw_ostream &OS, int OpIndex);
void expandCheckFunctionPredicate(raw_ostream &OS, StringRef MCInstFn,
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