[llvm] [RISCV] DAG combine (mul (add x, 1), y) -> vmadd (PR #71495)

[Craig Topper via llvm-commits]

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@@ -12423,6 +12423,45 @@ static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
   return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ false, Subtarget);
 }
 
+static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
+                                 const RISCVSubtarget &Subtarget) {
+  SDLoc DL(N);
+  EVT VT = N->getValueType(0);
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topperc wrote:

Need to check that the type is a vector so we don't do this to scalar operations. AArch64 doesn't have this because they have a scalar integer multiply accumulate instruction which RISC-V does not have.

https://github.com/llvm/llvm-project/pull/71495