[llvm] [RISCV][GlobalISel] Legalize G_ADD, G_SUB, G_AND, G_OR, G_XOR on RISC-V Vector Extension (PR #71400)

[Jiahan Xie via llvm-commits]

jiahanxie353 wrote:

> > > What's your insight into this behavior and what's your opinion on implementation @michaelmaitland @topperc ? I mean using them in-place works, but it's clumsy.
> > 
> > 
> > I experienced this too when I was playing around. Maybe we should do the in place definition, and a future patch can allow `legalIf`, `legalFor` , etc to be overloaded with something like T[].
> 
> Does `auto AllVecTys = {` work? The documentation for initializer list calls out auto as being special for C++17.

No it doesn't, I tried both. I also used gdb to print the address and data, the data are just garbage.

One thing I found was that [SPIRV](https://github.com/llvm/llvm-project/blob/c38ae74b48c1cb8aedf384686eaa05815d366609/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp#L160) is using this syntax.
So I guess our bug is not purely with `initializer_list` but with `scalable_vector` as well?

https://github.com/llvm/llvm-project/pull/71400