[llvm] [AArch64] Emit ST<OP> instruction when the return value has no use. (PR #72887)
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llvm-commits at lists.llvm.org
Mon Nov 20 08:12:45 PST 2023
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: Chia (sun-jacobi)
<details>
<summary>Changes</summary>
This PR fixed #<!-- -->69503.
---
Patch is 52.54 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/72887.diff
4 Files Affected:
- (modified) llvm/lib/Target/AArch64/AArch64InstrAtomics.td (+11-11)
- (modified) llvm/lib/Target/AArch64/AArch64InstrFormats.td (+98-54)
- (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.td (+40-50)
- (modified) llvm/test/CodeGen/AArch64/atomic-ops-lse.ll (+108-108)
``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
index 0002db52b1995c0..9c453eb506449b3 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
@@ -525,22 +525,22 @@ def CMP_SWAP_128_MONOTONIC : cmp_swap_128;
// v8.1 Atomic instructions:
let Predicates = [HasLSE] in {
- defm : LDOPregister_patterns<"LDADD", "atomic_load_add">;
- defm : LDOPregister_patterns<"LDSET", "atomic_load_or">;
- defm : LDOPregister_patterns<"LDEOR", "atomic_load_xor">;
- defm : LDOPregister_patterns<"LDCLR", "atomic_load_clr">;
- defm : LDOPregister_patterns<"LDSMAX", "atomic_load_max">;
- defm : LDOPregister_patterns<"LDSMIN", "atomic_load_min">;
- defm : LDOPregister_patterns<"LDUMAX", "atomic_load_umax">;
- defm : LDOPregister_patterns<"LDUMIN", "atomic_load_umin">;
- defm : LDOPregister_patterns<"SWP", "atomic_swap">;
+ defm : STLDOPregister_patterns<"ADD", "atomic_load_add">;
+ defm : STLDOPregister_patterns<"SET", "atomic_load_or">;
+ defm : STLDOPregister_patterns<"EOR", "atomic_load_xor">;
+ defm : STLDOPregister_patterns<"CLR", "atomic_load_clr">;
+ defm : STLDOPregister_patterns<"SMAX", "atomic_load_max">;
+ defm : STLDOPregister_patterns<"SMIN", "atomic_load_min">;
+ defm : STLDOPregister_patterns<"UMAX", "atomic_load_umax">;
+ defm : STLDOPregister_patterns<"UMIN", "atomic_load_umin">;
+ defm : SWPregister_patterns<"SWP", "atomic_swap">;
defm : CASregister_patterns<"CAS", "atomic_cmp_swap">;
// These two patterns are only needed for global isel, selection dag isel
// converts atomic load-sub into a sub and atomic load-add, and likewise for
// and -> clr.
- defm : LDOPregister_patterns_mod<"LDADD", "atomic_load_sub", "SUB">;
- defm : LDOPregister_patterns_mod<"LDCLR", "atomic_load_and", "ORN">;
+ defm : LDOPregister_patterns_mod<"ADD", "atomic_load_sub", "SUB">;
+ defm : LDOPregister_patterns_mod<"CLR", "atomic_load_and", "ORN">;
}
// v8.9a/v9.4a FEAT_LRCPC patterns
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index f88f5a240a1fd7f..0bb1babac57a2e3 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -11737,10 +11737,36 @@ multiclass Swap<bits<1> Acq, bits<1> Rel, string order> {
let Sz = 0b11, Acq = Acq, Rel = Rel in def X : BaseSWP<order, "", GPR64>;
}
+let Predicates = [HasLSE] in
+multiclass SWPpatterns<string inst, string suffix, string op, string size, dag SrcRHS, dag DstRHS> {
+ def : Pat<(!cast<PatFrag>(op#"_"#size#"_monotonic") GPR64sp:$Rn, SrcRHS),
+ (!cast<Instruction>(inst # suffix) DstRHS, GPR64sp:$Rn)>;
+ def : Pat<(!cast<PatFrag>(op#"_"#size#"_acquire") GPR64sp:$Rn, SrcRHS),
+ (!cast<Instruction>(inst # "A" # suffix) DstRHS, GPR64sp:$Rn)>;
+ def : Pat<(!cast<PatFrag>(op#"_"#size#"_release") GPR64sp:$Rn, SrcRHS),
+ (!cast<Instruction>(inst # "L" # suffix) DstRHS, GPR64sp:$Rn)>;
+ def : Pat<(!cast<PatFrag>(op#"_"#size#"_acq_rel") GPR64sp:$Rn, SrcRHS),
+ (!cast<Instruction>(inst # "AL" # suffix) DstRHS, GPR64sp:$Rn)>;
+ def : Pat<(!cast<PatFrag>(op#"_"#size#"_seq_cst") GPR64sp:$Rn, SrcRHS),
+ (!cast<Instruction>(inst # "AL" # suffix) DstRHS, GPR64sp:$Rn)>;
+}
+
+multiclass SWPregister_patterns_ord<string inst, string suffix, string op,
+ string size, dag RHS> {
+ defm : SWPpatterns<inst, suffix, op, size, RHS, RHS>;
+}
+
+multiclass SWPregister_patterns<string inst, string op> {
+ defm : SWPregister_patterns_ord<inst, "X", op, "64", (i64 GPR64:$Rm)>;
+ defm : SWPregister_patterns_ord<inst, "W", op, "32", (i32 GPR32:$Rm)>;
+ defm : SWPregister_patterns_ord<inst, "H", op, "16", (i32 GPR32:$Rm)>;
+ defm : SWPregister_patterns_ord<inst, "B", op, "8", (i32 GPR32:$Rm)>;
+}
+
+
let Predicates = [HasLSE], mayLoad = 1, mayStore = 1, hasSideEffects = 1 in
-class BaseLDOPregister<string op, string order, string size, RegisterClass RC>
- : I<(outs RC:$Rt),(ins RC:$Rs, GPR64sp:$Rn), "ld" # op # order # size,
- "\t$Rs, $Rt, [$Rn]","",[]>,
+class BaseSTLDOPregister<string op, string order, string size, RegisterClass RC, string prefix, string operand>
+ : I<(outs RC:$Rt),(ins RC:$Rs, GPR64sp:$Rn), !strconcat(prefix, op, order, size), operand,"",[]>,
Sched<[WriteAtomic]> {
bits<2> Sz;
bit Acq;
@@ -11763,38 +11789,80 @@ class BaseLDOPregister<string op, string order, string size, RegisterClass RC>
let Predicates = [HasLSE];
}
-multiclass LDOPregister<bits<3> opc, string op, bits<1> Acq, bits<1> Rel,
+
+multiclass STOPregister<bits<3> opc, string op, bits<1> Acq, bits<1> Rel, string order> {
+ let Rt = 0b11111, Acq = Acq, Rel = Rel, opc = opc in {
+ let Sz = 0b00 in def B : BaseSTLDOPregister<op, order, "b", GPR32, "st", "\t$Rs, [$Rn]">;
+ let Sz = 0b01 in def H : BaseSTLDOPregister<op, order, "h", GPR32, "st", "\t$Rs, [$Rn]">;
+ let Sz = 0b10 in def W : BaseSTLDOPregister<op, order, "", GPR32, "st", "\t$Rs, [$Rn]">;
+ let Sz = 0b11 in def X : BaseSTLDOPregister<op, order, "", GPR64, "st", "\t$Rs, [$Rn]">;
+ }
+}
+
+multiclass LDOPregister<bits<3> opc, string op, bits<1> Acq, bits<1> Rel, string order> {
+ let Acq = Acq, Rel = Rel, opc = opc in {
+ let Sz = 0b00 in def B : BaseSTLDOPregister<op, order, "b", GPR32, "ld", "\t$Rs, $Rt, [$Rn]">;
+ let Sz = 0b01 in def H : BaseSTLDOPregister<op, order, "h", GPR32, "ld", "\t$Rs, $Rt, [$Rn]">;
+ let Sz = 0b10 in def W : BaseSTLDOPregister<op, order, "", GPR32, "ld", "\t$Rs, $Rt, [$Rn]">;
+ let Sz = 0b11 in def X : BaseSTLDOPregister<op, order, "", GPR64, "ld", "\t$Rs, $Rt, [$Rn]">;
+ }
+}
+
+multiclass STLDOPregister<bits<3> opc, string op, bits<1> Acq, bits<1> Rel,
string order> {
- let Sz = 0b00, Acq = Acq, Rel = Rel, opc = opc in
- def B : BaseLDOPregister<op, order, "b", GPR32>;
- let Sz = 0b01, Acq = Acq, Rel = Rel, opc = opc in
- def H : BaseLDOPregister<op, order, "h", GPR32>;
- let Sz = 0b10, Acq = Acq, Rel = Rel, opc = opc in
- def W : BaseLDOPregister<op, order, "", GPR32>;
- let Sz = 0b11, Acq = Acq, Rel = Rel, opc = opc in
- def X : BaseLDOPregister<op, order, "", GPR64>;
+ defm "LD"#NAME : LDOPregister<opc, op, Acq, Rel, order>;
+ defm "ST"#NAME : STOPregister<opc, op, Acq, Rel, order>;
+}
+
+multiclass binary_atomic_op_noret<SDNode atomic_op> {
+ defm "_ret" : binary_atomic_op<atomic_op>;
+ let HasNoUse = true in
+ defm "_noret" : binary_atomic_op<atomic_op>;
+}
+
+defm atomic_load_add : binary_atomic_op_noret<atomic_load_add>;
+defm atomic_load_and : binary_atomic_op_noret<atomic_load_and>;
+defm atomic_load_max : binary_atomic_op_noret<atomic_load_max>;
+defm atomic_load_min : binary_atomic_op_noret<atomic_load_min>;
+defm atomic_load_clr : binary_atomic_op_noret<atomic_load_clr>;
+defm atomic_load_or : binary_atomic_op_noret<atomic_load_or>;
+defm atomic_load_sub : binary_atomic_op_noret<atomic_load_sub>;
+defm atomic_load_umax : binary_atomic_op_noret<atomic_load_umax>;
+defm atomic_load_umin : binary_atomic_op_noret<atomic_load_umin>;
+defm atomic_load_xor : binary_atomic_op_noret<atomic_load_xor>;
+
+let Predicates = [HasLSE] in
+multiclass STLDpatterns<string inst, string prefix, string suffix, string op, string ret,
+ string size, dag SrcRHS, dag DstRHS> {
+ def : Pat<(!cast<PatFrag>(op#"_"#ret#"_"#size#"_monotonic") GPR64sp:$Rn, SrcRHS),
+ (!cast<Instruction>(prefix # inst # suffix) DstRHS, GPR64sp:$Rn)>;
+ def : Pat<(!cast<PatFrag>(op#"_"#ret#"_"#size#"_acquire") GPR64sp:$Rn, SrcRHS),
+ (!cast<Instruction>(prefix # inst # "A" # suffix) DstRHS, GPR64sp:$Rn)>;
+ def : Pat<(!cast<PatFrag>(op#"_"#ret#"_"#size#"_release") GPR64sp:$Rn, SrcRHS),
+ (!cast<Instruction>(prefix # inst # "L" # suffix) DstRHS, GPR64sp:$Rn)>;
+ def : Pat<(!cast<PatFrag>(op#"_"#ret#"_"#size#"_acq_rel") GPR64sp:$Rn, SrcRHS),
+ (!cast<Instruction>(prefix # inst # "AL" # suffix) DstRHS, GPR64sp:$Rn)>;
+ def : Pat<(!cast<PatFrag>(op#"_"#ret#"_"#size#"_seq_cst") GPR64sp:$Rn, SrcRHS),
+ (!cast<Instruction>(prefix # inst # "AL" # suffix) DstRHS, GPR64sp:$Rn)>;
}
// Differing SrcRHS and DstRHS allow you to cover CLR & SUB by giving a more
// complex DAG for DstRHS.
-let Predicates = [HasLSE] in
+multiclass STLDOPregister_patterns_ord_dag<string inst, string suffix, string op,
+ string size, dag SrcRHS, dag DstRHS> {
+
+ defm : STLDpatterns<inst, "ST", suffix, op, "noret", size, SrcRHS, DstRHS>;
+ defm : STLDpatterns<inst, "LD", suffix, op, "ret", size, SrcRHS, DstRHS>;
+}
+
multiclass LDOPregister_patterns_ord_dag<string inst, string suffix, string op,
string size, dag SrcRHS, dag DstRHS> {
- def : Pat<(!cast<PatFrag>(op#"_"#size#"_monotonic") GPR64sp:$Rn, SrcRHS),
- (!cast<Instruction>(inst # suffix) DstRHS, GPR64sp:$Rn)>;
- def : Pat<(!cast<PatFrag>(op#"_"#size#"_acquire") GPR64sp:$Rn, SrcRHS),
- (!cast<Instruction>(inst # "A" # suffix) DstRHS, GPR64sp:$Rn)>;
- def : Pat<(!cast<PatFrag>(op#"_"#size#"_release") GPR64sp:$Rn, SrcRHS),
- (!cast<Instruction>(inst # "L" # suffix) DstRHS, GPR64sp:$Rn)>;
- def : Pat<(!cast<PatFrag>(op#"_"#size#"_acq_rel") GPR64sp:$Rn, SrcRHS),
- (!cast<Instruction>(inst # "AL" # suffix) DstRHS, GPR64sp:$Rn)>;
- def : Pat<(!cast<PatFrag>(op#"_"#size#"_seq_cst") GPR64sp:$Rn, SrcRHS),
- (!cast<Instruction>(inst # "AL" # suffix) DstRHS, GPR64sp:$Rn)>;
+ defm : STLDpatterns<inst, "LD", suffix, op, "ret", size, SrcRHS, DstRHS>;
}
-multiclass LDOPregister_patterns_ord<string inst, string suffix, string op,
+multiclass STLDOPregister_patterns_ord<string inst, string suffix, string op,
string size, dag RHS> {
- defm : LDOPregister_patterns_ord_dag<inst, suffix, op, size, RHS, RHS>;
+ defm : STLDOPregister_patterns_ord_dag<inst, suffix, op, size, RHS, RHS>;
}
multiclass LDOPregister_patterns_ord_mod<string inst, string suffix, string op,
@@ -11802,11 +11870,11 @@ multiclass LDOPregister_patterns_ord_mod<string inst, string suffix, string op,
defm : LDOPregister_patterns_ord_dag<inst, suffix, op, size, LHS, RHS>;
}
-multiclass LDOPregister_patterns<string inst, string op> {
- defm : LDOPregister_patterns_ord<inst, "X", op, "64", (i64 GPR64:$Rm)>;
- defm : LDOPregister_patterns_ord<inst, "W", op, "32", (i32 GPR32:$Rm)>;
- defm : LDOPregister_patterns_ord<inst, "H", op, "16", (i32 GPR32:$Rm)>;
- defm : LDOPregister_patterns_ord<inst, "B", op, "8", (i32 GPR32:$Rm)>;
+multiclass STLDOPregister_patterns<string inst, string op> {
+ defm : STLDOPregister_patterns_ord<inst, "X", op, "64", (i64 GPR64:$Rm)>;
+ defm : STLDOPregister_patterns_ord<inst, "W", op, "32", (i32 GPR32:$Rm)>;
+ defm : STLDOPregister_patterns_ord<inst, "H", op, "16", (i32 GPR32:$Rm)>;
+ defm : STLDOPregister_patterns_ord<inst, "B", op, "8", (i32 GPR32:$Rm)>;
}
multiclass LDOPregister_patterns_mod<string inst, string op, string mod> {
@@ -11855,30 +11923,6 @@ multiclass CASregister_patterns<string inst, string op> {
(i32 GPR32:$Rold), (i32 GPR32:$Rnew)>;
}
-let Predicates = [HasLSE] in
-class BaseSTOPregister<string asm, RegisterClass OP, Register Reg,
- Instruction inst> :
- InstAlias<asm # "\t$Rs, [$Rn]", (inst Reg, OP:$Rs, GPR64sp:$Rn)>;
-
-multiclass STOPregister<string asm, string instr> {
- def : BaseSTOPregister<asm # "lb", GPR32, WZR,
- !cast<Instruction>(instr # "LB")>;
- def : BaseSTOPregister<asm # "lh", GPR32, WZR,
- !cast<Instruction>(instr # "LH")>;
- def : BaseSTOPregister<asm # "l", GPR32, WZR,
- !cast<Instruction>(instr # "LW")>;
- def : BaseSTOPregister<asm # "l", GPR64, XZR,
- !cast<Instruction>(instr # "LX")>;
- def : BaseSTOPregister<asm # "b", GPR32, WZR,
- !cast<Instruction>(instr # "B")>;
- def : BaseSTOPregister<asm # "h", GPR32, WZR,
- !cast<Instruction>(instr # "H")>;
- def : BaseSTOPregister<asm, GPR32, WZR,
- !cast<Instruction>(instr # "W")>;
- def : BaseSTOPregister<asm, GPR64, XZR,
- !cast<Instruction>(instr # "X")>;
-}
-
class LoadStore64B_base<bits<3> opc, string asm_inst, string asm_ops,
dag iops, dag oops, list<dag> pat>
: I<oops, iops, asm_inst, asm_ops, "", pat>,
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index fb0ed425b1098ed..f9f8da1025573a6 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -2188,56 +2188,46 @@ defm SWPA : Swap<1, 0, "a">;
defm SWPL : Swap<0, 1, "l">;
defm SWPAL : Swap<1, 1, "al">;
-// v8.1 atomic LD<OP>(register). Performs load and then ST<OP>(register)
-defm LDADD : LDOPregister<0b000, "add", 0, 0, "">;
-defm LDADDA : LDOPregister<0b000, "add", 1, 0, "a">;
-defm LDADDL : LDOPregister<0b000, "add", 0, 1, "l">;
-defm LDADDAL : LDOPregister<0b000, "add", 1, 1, "al">;
-
-defm LDCLR : LDOPregister<0b001, "clr", 0, 0, "">;
-defm LDCLRA : LDOPregister<0b001, "clr", 1, 0, "a">;
-defm LDCLRL : LDOPregister<0b001, "clr", 0, 1, "l">;
-defm LDCLRAL : LDOPregister<0b001, "clr", 1, 1, "al">;
-
-defm LDEOR : LDOPregister<0b010, "eor", 0, 0, "">;
-defm LDEORA : LDOPregister<0b010, "eor", 1, 0, "a">;
-defm LDEORL : LDOPregister<0b010, "eor", 0, 1, "l">;
-defm LDEORAL : LDOPregister<0b010, "eor", 1, 1, "al">;
-
-defm LDSET : LDOPregister<0b011, "set", 0, 0, "">;
-defm LDSETA : LDOPregister<0b011, "set", 1, 0, "a">;
-defm LDSETL : LDOPregister<0b011, "set", 0, 1, "l">;
-defm LDSETAL : LDOPregister<0b011, "set", 1, 1, "al">;
-
-defm LDSMAX : LDOPregister<0b100, "smax", 0, 0, "">;
-defm LDSMAXA : LDOPregister<0b100, "smax", 1, 0, "a">;
-defm LDSMAXL : LDOPregister<0b100, "smax", 0, 1, "l">;
-defm LDSMAXAL : LDOPregister<0b100, "smax", 1, 1, "al">;
-
-defm LDSMIN : LDOPregister<0b101, "smin", 0, 0, "">;
-defm LDSMINA : LDOPregister<0b101, "smin", 1, 0, "a">;
-defm LDSMINL : LDOPregister<0b101, "smin", 0, 1, "l">;
-defm LDSMINAL : LDOPregister<0b101, "smin", 1, 1, "al">;
-
-defm LDUMAX : LDOPregister<0b110, "umax", 0, 0, "">;
-defm LDUMAXA : LDOPregister<0b110, "umax", 1, 0, "a">;
-defm LDUMAXL : LDOPregister<0b110, "umax", 0, 1, "l">;
-defm LDUMAXAL : LDOPregister<0b110, "umax", 1, 1, "al">;
-
-defm LDUMIN : LDOPregister<0b111, "umin", 0, 0, "">;
-defm LDUMINA : LDOPregister<0b111, "umin", 1, 0, "a">;
-defm LDUMINL : LDOPregister<0b111, "umin", 0, 1, "l">;
-defm LDUMINAL : LDOPregister<0b111, "umin", 1, 1, "al">;
-
-// v8.1 atomic ST<OP>(register) as aliases to "LD<OP>(register) when Rt=xZR"
-defm : STOPregister<"stadd","LDADD">; // STADDx
-defm : STOPregister<"stclr","LDCLR">; // STCLRx
-defm : STOPregister<"steor","LDEOR">; // STEORx
-defm : STOPregister<"stset","LDSET">; // STSETx
-defm : STOPregister<"stsmax","LDSMAX">;// STSMAXx
-defm : STOPregister<"stsmin","LDSMIN">;// STSMINx
-defm : STOPregister<"stumax","LDUMAX">;// STUMAXx
-defm : STOPregister<"stumin","LDUMIN">;// STUMINx
+// v8.1 atomic (ST|LD)<OP>(register).
+defm ADD : STLDOPregister<0b000, "add", 0, 0, "">;
+defm ADDA : STLDOPregister<0b000, "add", 1, 0, "a">;
+defm ADDL : STLDOPregister<0b000, "add", 0, 1, "l">;
+defm ADDAL : STLDOPregister<0b000, "add", 1, 1, "al">;
+
+defm CLR : STLDOPregister<0b001, "clr", 0, 0, "">;
+defm CLRA : STLDOPregister<0b001, "clr", 1, 0, "a">;
+defm CLRL : STLDOPregister<0b001, "clr", 0, 1, "l">;
+defm CLRAL : STLDOPregister<0b001, "clr", 1, 1, "al">;
+
+defm EOR : STLDOPregister<0b010, "eor", 0, 0, "">;
+defm EORA : STLDOPregister<0b010, "eor", 1, 0, "a">;
+defm EORL : STLDOPregister<0b010, "eor", 0, 1, "l">;
+defm EORAL : STLDOPregister<0b010, "eor", 1, 1, "al">;
+
+defm SET : STLDOPregister<0b011, "set", 0, 0, "">;
+defm SETA : STLDOPregister<0b011, "set", 1, 0, "a">;
+defm SETL : STLDOPregister<0b011, "set", 0, 1, "l">;
+defm SETAL : STLDOPregister<0b011, "set", 1, 1, "al">;
+
+defm SMAX : STLDOPregister<0b100, "smax", 0, 0, "">;
+defm SMAXA : STLDOPregister<0b100, "smax", 1, 0, "a">;
+defm SMAXL : STLDOPregister<0b100, "smax", 0, 1, "l">;
+defm SMAXAL : STLDOPregister<0b100, "smax", 1, 1, "al">;
+
+defm SMIN : STLDOPregister<0b101, "smin", 0, 0, "">;
+defm SMINA : STLDOPregister<0b101, "smin", 1, 0, "a">;
+defm SMINL : STLDOPregister<0b101, "smin", 0, 1, "l">;
+defm SMINAL : STLDOPregister<0b101, "smin", 1, 1, "al">;
+
+defm UMAX : STLDOPregister<0b110, "umax", 0, 0, "">;
+defm UMAXA : STLDOPregister<0b110, "umax", 1, 0, "a">;
+defm UMAXL : STLDOPregister<0b110, "umax", 0, 1, "l">;
+defm UMAXAL : STLDOPregister<0b110, "umax", 1, 1, "al">;
+
+defm UMIN : STLDOPregister<0b111, "umin", 0, 0, "">;
+defm UMINA : STLDOPregister<0b111, "umin", 1, 0, "a">;
+defm UMINL : STLDOPregister<0b111, "umin", 0, 1, "l">;
+defm UMINAL : STLDOPregister<0b111, "umin", 1, 1, "al">;
// v8.5 Memory Tagging Extension
let Predicates = [HasMTE] in {
diff --git a/llvm/test/CodeGen/AArch64/atomic-ops-lse.ll b/llvm/test/CodeGen/AArch64/atomic-ops-lse.ll
index 70f3b5cc488ea8b..c624d447ce99c48 100644
--- a/llvm/test/CodeGen/AArch64/atomic-ops-lse.ll
+++ b/llvm/test/CodeGen/AArch64/atomic-ops-lse.ll
@@ -114,7 +114,7 @@ define dso_local void @test_atomic_load_add_i32_noret(i32 %offset) nounwind {
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
-; CHECK: ldaddal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK: staddal w0, [x[[ADDR]]]
; CHECK-NOT: dmb
ret void
}
@@ -134,7 +134,7 @@ define dso_local void @test_atomic_load_add_i64_noret(i64 %offset) nounwind {
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
-; CHECK: ldaddal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK: staddal x0, [x[[ADDR]]]
; CHECK-NOT: dmb
ret void
}
@@ -238,7 +238,7 @@ define dso_local void @test_atomic_load_or_i32_noret(i32 %offset) nounwind {
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
-; CHECK: ldsetal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK: stsetal w0, [x[[ADDR]]]
; CHECK-NOT: dmb
ret void
}
@@ -258,7 +258,7 @@ define dso_local void @test_atomic_load_or_i64_noret(i64 %offset) nounwind {
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
-; CHECK: ldsetal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK: stsetal x0, [x[[ADDR]]]
; CHECK-NOT: dmb
ret void
}
@@ -362,7 +362,7 @@ define dso_local void @test_atomic_load_xor_i32_noret(i32 %offset) nounwind {
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
-; CHECK: ldeoral w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK: steoral w0, [x[[ADDR]]]
; CHECK-NOT: dmb
ret void
}
@@ -382,7 +382,7 @@ define dso_local void @test_atomic_load_xor_i64_noret(i64 %offset) nounwind {
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
-; CHECK: ldeoral x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK: steoral x0, [x[[ADDR]]]
; CHECK-NOT: dmb
ret void
}
@@ -517,7 +517,7 @@ define dso_local void @test_atomic_load_min_i32_noret(i32 %offset) nounwind {
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
-; CHECK: ldsminal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK: stsminal w0, [x[[ADDR]]]
; CHECK-NOT: dmb
ret void
}
@@ -542,7 +542,7 @@ define dso_local void @test_atomic_load_min_i64_noret(i64 %offset) nounwind {
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
-; CHECK: ldsminal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK: stsminal x0, [x[[ADDR]]]
; CHECK-NOT: dmb
ret void
}
@@ -677,7 +677,7 @@ define dso_local void @test_atomic_load_umin_i32_noret(i32 %offset) nounwind {
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
-; CHECK: lduminal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK: stuminal w0, [...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/72887
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