[llvm] 40e46b6 - [SLP]Do not emit int bitcast after minbitwidth analysis.
Alexey Bataev via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 20 06:27:52 PST 2023
Author: Alexey Bataev
Date: 2023-11-20T06:25:17-08:00
New Revision: 40e46b6effd38ee93c0de76f1b898230209bca1c
URL: https://github.com/llvm/llvm-project/commit/40e46b6effd38ee93c0de76f1b898230209bca1c
DIFF: https://github.com/llvm/llvm-project/commit/40e46b6effd38ee93c0de76f1b898230209bca1c.diff
LOG: [SLP]Do not emit int bitcast after minbitwidth analysis.
No need to emit bitcat op for integer operands if it is detected that
after minbitwidth analysis the type is the same.
Added:
llvm/test/Transforms/SLPVectorizer/X86/int-bitcast-minbitwidth.ll
Modified:
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index a5271934a60c6b9..2aedc9b4054d429 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -11338,7 +11338,9 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool PostponedPHIs) {
VecOpcode = It->second.second ? Instruction::SExt : Instruction::ZExt;
}
}
- Value *V = Builder.CreateCast(VecOpcode, InVec, VecTy);
+ Value *V = (VecOpcode != ShuffleOrOp && VecOpcode == Instruction::BitCast)
+ ? InVec
+ : Builder.CreateCast(VecOpcode, InVec, VecTy);
V = FinalShuffle(V, E, VecTy, IsSigned);
E->VectorizedValue = V;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/int-bitcast-minbitwidth.ll b/llvm/test/Transforms/SLPVectorizer/X86/int-bitcast-minbitwidth.ll
new file mode 100644
index 000000000000000..a2bebef8af8732c
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/int-bitcast-minbitwidth.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+define void @t() {
+; CHECK-LABEL: define void @t() {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = or i32 0, 0
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[TMP0]], 65535
+; CHECK-NEXT: store i32 [[TMP1]], ptr null, align 4
+; CHECK-NEXT: ret void
+;
+entry:
+ %conv12.1.i = trunc i64 0 to i32
+ %mul.i.1.i = mul i32 %conv12.1.i, 0
+ %conv12.i = trunc i64 0 to i32
+ %mul.i.i = mul i32 %conv12.i, 0
+ %conv14104.i = or i32 %mul.i.1.i, %mul.i.i
+ %conv12.1.i.1 = trunc i64 0 to i32
+ %mul.i.1.i.1 = mul i32 %conv12.1.i.1, 0
+ %conv12.i.1 = trunc i64 0 to i32
+ %mul.i.i.1 = mul i32 %conv12.i.1, 0
+ %conv14104.i.1 = or i32 %mul.i.1.i.1, %mul.i.i.1
+ %0 = or i32 %conv14104.i, %conv14104.i.1
+ %1 = and i32 %0, 65535
+ store i32 %1, ptr null, align 4
+ ret void
+}
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