[llvm] [RISCV] Minimally modify incoming state in transferBefore (PR #72352)
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Sun Nov 19 22:00:49 PST 2023
https://github.com/lukel97 updated https://github.com/llvm/llvm-project/pull/72352
>From fde2f52cb514f405c14b831c866fddd79032e769 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Wed, 15 Nov 2023 14:19:19 +0800
Subject: [PATCH 1/3] [RISCV] Minimally modify incoming state in transferBefore
transferBefore currently takes an incoming state and an instruction, computes
the new state needed for the instruction, and then modifies that new state to
be more similar to the incoming state.
This patch reverses the approach by instead taking the incoming state and
modifying only the bits that are demanded by the instruction.
I find this makes things slightly easier to reason about. It also us to use the
x0, x0 form in more places, in particular with vmv.x.s since we're no longer
relying on isScalarInsertInstr, but instead reusing the logic in getDemanded.
I haven't had a chance to check, but hopefully this might also address some of
the regressions seen in #71501.
---
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 102 ++--
.../RISCV/rvv/fixed-vectors-extract-i1.ll | 20 +-
.../RISCV/rvv/fixed-vectors-masked-gather.ll | 511 +++++++-----------
.../RISCV/rvv/fixed-vectors-masked-scatter.ll | 84 +--
.../RISCV/rvv/fixed-vectors-reduction-fp.ll | 42 +-
.../RISCV/rvv/fixed-vectors-reduction-int.ll | 48 +-
.../RISCV/rvv/fixed-vectors-unaligned.ll | 20 +-
.../RISCV/rvv/vreductions-fp-sdnode.ll | 16 +-
.../CodeGen/RISCV/rvv/vreductions-int-vp.ll | 8 +-
.../test/CodeGen/RISCV/rvv/vreductions-int.ll | 24 +-
.../RISCV/rvv/vsetvli-insert-crossbb.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll | 3 +-
.../CodeGen/RISCV/rvv/vsetvli-regression.ll | 2 +-
13 files changed, 374 insertions(+), 510 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index 3bbc85d836c3f4a..8483b770353a84f 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -479,6 +479,8 @@ class VSETVLIInfo {
unsigned getSEW() const { return SEW; }
RISCVII::VLMUL getVLMUL() const { return VLMul; }
+ bool getTailAgnostic() const { return TailAgnostic; }
+ bool getMaskAgnostic() const { return MaskAgnostic; }
bool hasNonZeroAVL(const MachineRegisterInfo &MRI) const {
if (hasAVLImm())
@@ -1013,73 +1015,77 @@ bool RISCVInsertVSETVLI::needVSETVLI(const MachineInstr &MI,
return true;
}
-// Given an incoming state reaching MI, modifies that state so that it is minimally
-// compatible with MI. The resulting state is guaranteed to be semantically legal
-// for MI, but may not be the state requested by MI.
+// Given an incoming state reaching MI, minimally modifies that state so that it
+// is compatible with MI. The resulting state is guaranteed to be semantically
+// legal for MI, but may not be the state requested by MI.
void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
const MachineInstr &MI) const {
uint64_t TSFlags = MI.getDesc().TSFlags;
if (!RISCVII::hasSEWOp(TSFlags))
return;
- const VSETVLIInfo NewInfo = computeInfoForInstr(MI, TSFlags, MRI);
+ VSETVLIInfo NewInfo = computeInfoForInstr(MI, TSFlags, MRI);
assert(NewInfo.isValid() && !NewInfo.isUnknown());
if (Info.isValid() && !needVSETVLI(MI, NewInfo, Info))
return;
- const VSETVLIInfo PrevInfo = Info;
- Info = NewInfo;
+ if (Info.hasSEWLMULRatioOnly() || !Info.isValid() || Info.isUnknown())
+ Info = NewInfo;
- if (!RISCVII::hasVLOp(TSFlags))
- return;
+ DemandedFields Demanded = getDemanded(MI, MRI, ST);
// If we don't use LMUL or the SEW/LMUL ratio, then adjust LMUL so that we
// maintain the SEW/LMUL ratio. This allows us to eliminate VL toggles in more
// places.
- DemandedFields Demanded = getDemanded(MI, MRI, ST);
- if (!Demanded.LMUL && !Demanded.SEWLMULRatio && PrevInfo.isValid() &&
- !PrevInfo.isUnknown()) {
- if (auto NewVLMul = RISCVVType::getSameRatioLMUL(
- PrevInfo.getSEW(), PrevInfo.getVLMUL(), Info.getSEW()))
- Info.setVLMul(*NewVLMul);
- }
-
- // If we only demand VL zeroness (i.e. vmv.s.x and vmv.x.s), then there are
- // only two behaviors, VL = 0 and VL > 0. We can discard the user requested
- // AVL and just use the last one if we can prove it equally zero. This
- // removes a vsetvli entirely if the types match or allows use of cheaper avl
- // preserving variant if VLMAX doesn't change. If VLMAX might change, we
- // couldn't use the 'vsetvli x0, x0, vtype" variant, so we avoid the transform
- // to prevent extending live range of an avl register operand.
- // TODO: We can probably relax this for immediates.
- if (Demanded.VLZeroness && !Demanded.VLAny && PrevInfo.isValid() &&
- PrevInfo.hasEquallyZeroAVL(Info, *MRI) && Info.hasSameVLMAX(PrevInfo)) {
- if (PrevInfo.hasAVLImm())
- Info.setAVLImm(PrevInfo.getAVLImm());
- else
- Info.setAVLReg(PrevInfo.getAVLReg());
- return;
+ if (!Demanded.LMUL && !Demanded.SEWLMULRatio && Info.isValid() &&
+ !Info.isUnknown()) {
+ if (auto SameRatioLMUL = RISCVVType::getSameRatioLMUL(
+ Info.getSEW(), Info.getVLMUL(), NewInfo.getSEW())) {
+ NewInfo.setVLMul(*SameRatioLMUL);
+ Demanded.LMUL = true;
+ }
}
- // If AVL is defined by a vsetvli with the same VLMAX, we can
- // replace the AVL operand with the AVL of the defining vsetvli.
- // We avoid general register AVLs to avoid extending live ranges
- // without being sure we can kill the original source reg entirely.
- if (!Info.hasAVLReg() || !Info.getAVLReg().isVirtual())
- return;
- MachineInstr *DefMI = MRI->getVRegDef(Info.getAVLReg());
- if (!DefMI || !isVectorConfigInstr(*DefMI))
- return;
+ // If AVL is defined by a vsetvli with the same VLMAX, we can replace the AVL
+ // operand with the AVL of the defining vsetvli. We avoid general register
+ // AVLs to avoid extending live ranges without being sure we can kill the
+ // original source reg entirely.
+ if (RISCVII::hasVLOp(TSFlags) && NewInfo.hasAVLReg() &&
+ NewInfo.getAVLReg().isVirtual()) {
+ MachineInstr *DefMI = MRI->getVRegDef(NewInfo.getAVLReg());
+ if (DefMI && isVectorConfigInstr(*DefMI)) {
+ VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
+ if (DefInfo.hasSameVLMAX(NewInfo) &&
+ (DefInfo.hasAVLImm() || DefInfo.getAVLReg() == RISCV::X0)) {
+ if (DefInfo.hasAVLImm())
+ NewInfo.setAVLImm(DefInfo.getAVLImm());
+ else
+ NewInfo.setAVLReg(DefInfo.getAVLReg());
+ }
+ }
+ }
- VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
- if (DefInfo.hasSameVLMAX(Info) &&
- (DefInfo.hasAVLImm() || DefInfo.getAVLReg() == RISCV::X0)) {
- if (DefInfo.hasAVLImm())
- Info.setAVLImm(DefInfo.getAVLImm());
+ // If MI only demands that VL has the same zeroness, we only need to set the
+ // AVL if the zeroness differs, or if VLMAX changes (since that prevents us
+ // from using vsetvli x0, x0).
+ bool CanUseX0X0Form =
+ Info.hasEquallyZeroAVL(NewInfo, *MRI) && Info.hasSameVLMAX(NewInfo);
+ if (Demanded.VLAny || (Demanded.VLZeroness && !CanUseX0X0Form)) {
+ if (NewInfo.hasAVLImm())
+ Info.setAVLImm(NewInfo.getAVLImm());
else
- Info.setAVLReg(DefInfo.getAVLReg());
- return;
- }
+ Info.setAVLReg(NewInfo.getAVLReg());
+ }
+
+ Info.setVTYPE(
+ ((Demanded.LMUL || Demanded.SEWLMULRatio) ? NewInfo : Info).getVLMUL(),
+ ((Demanded.SEW || Demanded.SEWLMULRatio) ? NewInfo : Info).getSEW(),
+ // Prefer tail/mask agnostic since it can be relaxed to undisturbed later
+ // if needed.
+ (Demanded.TailPolicy ? NewInfo : Info).getTailAgnostic() ||
+ NewInfo.getTailAgnostic(),
+ (Demanded.MaskPolicy ? NewInfo : Info).getMaskAgnostic() ||
+ NewInfo.getMaskAgnostic());
}
// Given a state with which we evaluated MI (see transferBefore above for why
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
index 9d689c732d7999f..7ad01ceea33b154 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
@@ -106,7 +106,7 @@ define i1 @extractelt_v16i1(ptr %x, i64 %idx) nounwind {
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vle8.v v8, (a0)
; RV32-NEXT: vmseq.vi v8, v8, 0
-; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: srl a0, a0, a1
; RV32-NEXT: andi a0, a0, 1
@@ -117,7 +117,7 @@ define i1 @extractelt_v16i1(ptr %x, i64 %idx) nounwind {
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vle8.v v8, (a0)
; RV64-NEXT: vmseq.vi v8, v8, 0
-; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: srl a0, a0, a1
; RV64-NEXT: andi a0, a0, 1
@@ -128,7 +128,7 @@ define i1 @extractelt_v16i1(ptr %x, i64 %idx) nounwind {
; RV32ZBS-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32ZBS-NEXT: vle8.v v8, (a0)
; RV32ZBS-NEXT: vmseq.vi v8, v8, 0
-; RV32ZBS-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; RV32ZBS-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV32ZBS-NEXT: vmv.x.s a0, v8
; RV32ZBS-NEXT: bext a0, a0, a1
; RV32ZBS-NEXT: ret
@@ -138,7 +138,7 @@ define i1 @extractelt_v16i1(ptr %x, i64 %idx) nounwind {
; RV64ZBS-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64ZBS-NEXT: vle8.v v8, (a0)
; RV64ZBS-NEXT: vmseq.vi v8, v8, 0
-; RV64ZBS-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; RV64ZBS-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64ZBS-NEXT: vmv.x.s a0, v8
; RV64ZBS-NEXT: bext a0, a0, a1
; RV64ZBS-NEXT: ret
@@ -155,7 +155,7 @@ define i1 @extractelt_v32i1(ptr %x, i64 %idx) nounwind {
; RV32-NEXT: vsetvli zero, a2, e8, m2, ta, ma
; RV32-NEXT: vle8.v v8, (a0)
; RV32-NEXT: vmseq.vi v10, v8, 0
-; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; RV32-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: srl a0, a0, a1
; RV32-NEXT: andi a0, a0, 1
@@ -167,7 +167,7 @@ define i1 @extractelt_v32i1(ptr %x, i64 %idx) nounwind {
; RV64-NEXT: vsetvli zero, a2, e8, m2, ta, ma
; RV64-NEXT: vle8.v v8, (a0)
; RV64-NEXT: vmseq.vi v10, v8, 0
-; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; RV64-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; RV64-NEXT: vmv.x.s a0, v10
; RV64-NEXT: srl a0, a0, a1
; RV64-NEXT: andi a0, a0, 1
@@ -179,7 +179,7 @@ define i1 @extractelt_v32i1(ptr %x, i64 %idx) nounwind {
; RV32ZBS-NEXT: vsetvli zero, a2, e8, m2, ta, ma
; RV32ZBS-NEXT: vle8.v v8, (a0)
; RV32ZBS-NEXT: vmseq.vi v10, v8, 0
-; RV32ZBS-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; RV32ZBS-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; RV32ZBS-NEXT: vmv.x.s a0, v10
; RV32ZBS-NEXT: bext a0, a0, a1
; RV32ZBS-NEXT: ret
@@ -190,7 +190,7 @@ define i1 @extractelt_v32i1(ptr %x, i64 %idx) nounwind {
; RV64ZBS-NEXT: vsetvli zero, a2, e8, m2, ta, ma
; RV64ZBS-NEXT: vle8.v v8, (a0)
; RV64ZBS-NEXT: vmseq.vi v10, v8, 0
-; RV64ZBS-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; RV64ZBS-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; RV64ZBS-NEXT: vmv.x.s a0, v10
; RV64ZBS-NEXT: bext a0, a0, a1
; RV64ZBS-NEXT: ret
@@ -221,7 +221,7 @@ define i1 @extractelt_v64i1(ptr %x, i64 %idx) nounwind {
; RV64-NEXT: vsetvli zero, a2, e8, m4, ta, ma
; RV64-NEXT: vle8.v v8, (a0)
; RV64-NEXT: vmseq.vi v12, v8, 0
-; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; RV64-NEXT: vsetvli zero, a2, e64, m4, ta, ma
; RV64-NEXT: vmv.x.s a0, v12
; RV64-NEXT: srl a0, a0, a1
; RV64-NEXT: andi a0, a0, 1
@@ -246,7 +246,7 @@ define i1 @extractelt_v64i1(ptr %x, i64 %idx) nounwind {
; RV64ZBS-NEXT: vsetvli zero, a2, e8, m4, ta, ma
; RV64ZBS-NEXT: vle8.v v8, (a0)
; RV64ZBS-NEXT: vmseq.vi v12, v8, 0
-; RV64ZBS-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; RV64ZBS-NEXT: vsetvli zero, a2, e64, m4, ta, ma
; RV64ZBS-NEXT: vmv.x.s a0, v12
; RV64ZBS-NEXT: bext a0, a0, a1
; RV64ZBS-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
index d74fd6cd3f03470..8c73f7eea4cd28a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
@@ -543,9 +543,8 @@ define <4 x i8> @mgather_truemask_v4i8(<4 x ptr> %ptrs, <4 x i8> %passthru) {
; RV64ZVE32F-NEXT: .LBB9_6: # %cond.load1
; RV64ZVE32F-NEXT: ld a2, 8(a0)
; RV64ZVE32F-NEXT: lbu a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: andi a2, a1, 4
; RV64ZVE32F-NEXT: beqz a2, .LBB9_3
@@ -1267,9 +1266,8 @@ define <4 x i16> @mgather_truemask_v4i16(<4 x ptr> %ptrs, <4 x i16> %passthru) {
; RV64ZVE32F-NEXT: .LBB20_6: # %cond.load1
; RV64ZVE32F-NEXT: ld a2, 8(a0)
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: andi a2, a1, 4
; RV64ZVE32F-NEXT: beqz a2, .LBB20_3
@@ -2351,9 +2349,8 @@ define <4 x i32> @mgather_truemask_v4i32(<4 x ptr> %ptrs, <4 x i32> %passthru) {
; RV64ZVE32F-NEXT: .LBB32_6: # %cond.load1
; RV64ZVE32F-NEXT: ld a2, 8(a0)
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: andi a2, a1, 4
; RV64ZVE32F-NEXT: beqz a2, .LBB32_3
@@ -3844,7 +3841,7 @@ define <4 x i64> @mgather_truemask_v4i64(<4 x ptr> %ptrs, <4 x i64> %passthru) {
; RV32ZVE32F-NEXT: vmv.x.s a6, v9
; RV32ZVE32F-NEXT: bnez zero, .LBB45_5
; RV32ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a3, v8
; RV32ZVE32F-NEXT: lw a2, 4(a3)
; RV32ZVE32F-NEXT: lw a3, 0(a3)
@@ -4265,12 +4262,12 @@ define <8 x i64> @mgather_baseidx_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV32ZVE32F-NEXT: vsext.vf4 v10, v8
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s t0, v0
; RV32ZVE32F-NEXT: andi a1, t0, 1
; RV32ZVE32F-NEXT: beqz a1, .LBB48_7
; RV32ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a3, v8
; RV32ZVE32F-NEXT: lw a1, 4(a3)
; RV32ZVE32F-NEXT: lw a3, 0(a3)
@@ -4539,12 +4536,12 @@ define <8 x i64> @mgather_baseidx_sext_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8
; RV32ZVE32F-NEXT: vsext.vf4 v10, v8
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s t0, v0
; RV32ZVE32F-NEXT: andi a1, t0, 1
; RV32ZVE32F-NEXT: beqz a1, .LBB49_7
; RV32ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a3, v8
; RV32ZVE32F-NEXT: lw a1, 4(a3)
; RV32ZVE32F-NEXT: lw a3, 0(a3)
@@ -4815,12 +4812,12 @@ define <8 x i64> @mgather_baseidx_zext_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8
; RV32ZVE32F-NEXT: vzext.vf4 v10, v8
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s t0, v0
; RV32ZVE32F-NEXT: andi a1, t0, 1
; RV32ZVE32F-NEXT: beqz a1, .LBB50_7
; RV32ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a3, v8
; RV32ZVE32F-NEXT: lw a1, 4(a3)
; RV32ZVE32F-NEXT: lw a3, 0(a3)
@@ -5098,12 +5095,12 @@ define <8 x i64> @mgather_baseidx_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <8 x i
; RV32ZVE32F-NEXT: vsext.vf2 v10, v8
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s t0, v0
; RV32ZVE32F-NEXT: andi a1, t0, 1
; RV32ZVE32F-NEXT: beqz a1, .LBB51_7
; RV32ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a3, v8
; RV32ZVE32F-NEXT: lw a1, 4(a3)
; RV32ZVE32F-NEXT: lw a3, 0(a3)
@@ -5373,12 +5370,12 @@ define <8 x i64> @mgather_baseidx_sext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV32ZVE32F-NEXT: vsext.vf2 v10, v8
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s t0, v0
; RV32ZVE32F-NEXT: andi a1, t0, 1
; RV32ZVE32F-NEXT: beqz a1, .LBB52_7
; RV32ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a3, v8
; RV32ZVE32F-NEXT: lw a1, 4(a3)
; RV32ZVE32F-NEXT: lw a3, 0(a3)
@@ -5650,12 +5647,12 @@ define <8 x i64> @mgather_baseidx_zext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV32ZVE32F-NEXT: vzext.vf2 v10, v8
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s t0, v0
; RV32ZVE32F-NEXT: andi a1, t0, 1
; RV32ZVE32F-NEXT: beqz a1, .LBB53_7
; RV32ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a3, v8
; RV32ZVE32F-NEXT: lw a1, 4(a3)
; RV32ZVE32F-NEXT: lw a3, 0(a3)
@@ -5934,12 +5931,12 @@ define <8 x i64> @mgather_baseidx_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <8 x i
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s t0, v0
; RV32ZVE32F-NEXT: andi a1, t0, 1
; RV32ZVE32F-NEXT: beqz a1, .LBB54_7
; RV32ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a3, v8
; RV32ZVE32F-NEXT: lw a1, 4(a3)
; RV32ZVE32F-NEXT: lw a3, 0(a3)
@@ -6207,12 +6204,12 @@ define <8 x i64> @mgather_baseidx_sext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s t0, v0
; RV32ZVE32F-NEXT: andi a1, t0, 1
; RV32ZVE32F-NEXT: beqz a1, .LBB55_7
; RV32ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a3, v8
; RV32ZVE32F-NEXT: lw a1, 4(a3)
; RV32ZVE32F-NEXT: lw a3, 0(a3)
@@ -6481,12 +6478,12 @@ define <8 x i64> @mgather_baseidx_zext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s t0, v0
; RV32ZVE32F-NEXT: andi a1, t0, 1
; RV32ZVE32F-NEXT: beqz a1, .LBB56_7
; RV32ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a3, v8
; RV32ZVE32F-NEXT: lw a1, 4(a3)
; RV32ZVE32F-NEXT: lw a3, 0(a3)
@@ -6778,12 +6775,12 @@ define <8 x i64> @mgather_baseidx_v8i64(ptr %base, <8 x i64> %idxs, <8 x i1> %m,
; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, a4
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s t0, v0
; RV32ZVE32F-NEXT: andi a1, t0, 1
; RV32ZVE32F-NEXT: beqz a1, .LBB57_7
; RV32ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a2, v8
; RV32ZVE32F-NEXT: lw a1, 4(a2)
; RV32ZVE32F-NEXT: lw a2, 0(a2)
@@ -7215,9 +7212,8 @@ define <4 x half> @mgather_truemask_v4f16(<4 x ptr> %ptrs, <4 x half> %passthru)
; RV64ZVE32F-NEXT: .LBB61_6: # %cond.load1
; RV64ZVE32F-NEXT: ld a2, 8(a0)
; RV64ZVE32F-NEXT: flh fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: andi a2, a1, 4
; RV64ZVE32F-NEXT: beqz a2, .LBB61_3
@@ -8173,9 +8169,8 @@ define <4 x float> @mgather_truemask_v4f32(<4 x ptr> %ptrs, <4 x float> %passthr
; RV64ZVE32F-NEXT: .LBB71_6: # %cond.load1
; RV64ZVE32F-NEXT: ld a2, 8(a0)
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: andi a2, a1, 4
; RV64ZVE32F-NEXT: beqz a2, .LBB71_3
@@ -9652,7 +9647,7 @@ define <4 x double> @mgather_truemask_v4f64(<4 x ptr> %ptrs, <4 x double> %passt
; RV32ZVE32F-NEXT: fsd fa3, 24(a0)
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB84_6: # %cond.load
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a2, v8
; RV32ZVE32F-NEXT: fld fa0, 0(a2)
; RV32ZVE32F-NEXT: andi a2, a1, 2
@@ -9964,7 +9959,7 @@ define <8 x double> @mgather_baseidx_v8i8_v8f64(ptr %base, <8 x i8> %idxs, <8 x
; RV32ZVE32F-NEXT: vsext.vf4 v10, v8
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
; RV32ZVE32F-NEXT: andi a2, a1, 1
; RV32ZVE32F-NEXT: bnez a2, .LBB87_10
@@ -10005,7 +10000,7 @@ define <8 x double> @mgather_baseidx_v8i8_v8f64(ptr %base, <8 x i8> %idxs, <8 x
; RV32ZVE32F-NEXT: fsd fa7, 56(a0)
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB87_10: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a2, v8
; RV32ZVE32F-NEXT: fld fa0, 0(a2)
; RV32ZVE32F-NEXT: andi a2, a1, 2
@@ -10179,7 +10174,7 @@ define <8 x double> @mgather_baseidx_sext_v8i8_v8f64(ptr %base, <8 x i8> %idxs,
; RV32ZVE32F-NEXT: vsext.vf4 v10, v8
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
; RV32ZVE32F-NEXT: andi a2, a1, 1
; RV32ZVE32F-NEXT: bnez a2, .LBB88_10
@@ -10220,7 +10215,7 @@ define <8 x double> @mgather_baseidx_sext_v8i8_v8f64(ptr %base, <8 x i8> %idxs,
; RV32ZVE32F-NEXT: fsd fa7, 56(a0)
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB88_10: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a2, v8
; RV32ZVE32F-NEXT: fld fa0, 0(a2)
; RV32ZVE32F-NEXT: andi a2, a1, 2
@@ -10396,7 +10391,7 @@ define <8 x double> @mgather_baseidx_zext_v8i8_v8f64(ptr %base, <8 x i8> %idxs,
; RV32ZVE32F-NEXT: vzext.vf4 v10, v8
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
; RV32ZVE32F-NEXT: andi a2, a1, 1
; RV32ZVE32F-NEXT: bnez a2, .LBB89_10
@@ -10437,7 +10432,7 @@ define <8 x double> @mgather_baseidx_zext_v8i8_v8f64(ptr %base, <8 x i8> %idxs,
; RV32ZVE32F-NEXT: fsd fa7, 56(a0)
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB89_10: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a2, v8
; RV32ZVE32F-NEXT: fld fa0, 0(a2)
; RV32ZVE32F-NEXT: andi a2, a1, 2
@@ -10620,7 +10615,7 @@ define <8 x double> @mgather_baseidx_v8i16_v8f64(ptr %base, <8 x i16> %idxs, <8
; RV32ZVE32F-NEXT: vsext.vf2 v10, v8
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
; RV32ZVE32F-NEXT: andi a2, a1, 1
; RV32ZVE32F-NEXT: bnez a2, .LBB90_10
@@ -10661,7 +10656,7 @@ define <8 x double> @mgather_baseidx_v8i16_v8f64(ptr %base, <8 x i16> %idxs, <8
; RV32ZVE32F-NEXT: fsd fa7, 56(a0)
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB90_10: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a2, v8
; RV32ZVE32F-NEXT: fld fa0, 0(a2)
; RV32ZVE32F-NEXT: andi a2, a1, 2
@@ -10836,7 +10831,7 @@ define <8 x double> @mgather_baseidx_sext_v8i16_v8f64(ptr %base, <8 x i16> %idxs
; RV32ZVE32F-NEXT: vsext.vf2 v10, v8
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
; RV32ZVE32F-NEXT: andi a2, a1, 1
; RV32ZVE32F-NEXT: bnez a2, .LBB91_10
@@ -10877,7 +10872,7 @@ define <8 x double> @mgather_baseidx_sext_v8i16_v8f64(ptr %base, <8 x i16> %idxs
; RV32ZVE32F-NEXT: fsd fa7, 56(a0)
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB91_10: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a2, v8
; RV32ZVE32F-NEXT: fld fa0, 0(a2)
; RV32ZVE32F-NEXT: andi a2, a1, 2
@@ -11054,7 +11049,7 @@ define <8 x double> @mgather_baseidx_zext_v8i16_v8f64(ptr %base, <8 x i16> %idxs
; RV32ZVE32F-NEXT: vzext.vf2 v10, v8
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
; RV32ZVE32F-NEXT: andi a2, a1, 1
; RV32ZVE32F-NEXT: bnez a2, .LBB92_10
@@ -11095,7 +11090,7 @@ define <8 x double> @mgather_baseidx_zext_v8i16_v8f64(ptr %base, <8 x i16> %idxs
; RV32ZVE32F-NEXT: fsd fa7, 56(a0)
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB92_10: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a2, v8
; RV32ZVE32F-NEXT: fld fa0, 0(a2)
; RV32ZVE32F-NEXT: andi a2, a1, 2
@@ -11279,7 +11274,7 @@ define <8 x double> @mgather_baseidx_v8i32_v8f64(ptr %base, <8 x i32> %idxs, <8
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
; RV32ZVE32F-NEXT: andi a2, a1, 1
; RV32ZVE32F-NEXT: bnez a2, .LBB93_10
@@ -11320,7 +11315,7 @@ define <8 x double> @mgather_baseidx_v8i32_v8f64(ptr %base, <8 x i32> %idxs, <8
; RV32ZVE32F-NEXT: fsd fa7, 56(a0)
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB93_10: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a2, v8
; RV32ZVE32F-NEXT: fld fa0, 0(a2)
; RV32ZVE32F-NEXT: andi a2, a1, 2
@@ -11493,7 +11488,7 @@ define <8 x double> @mgather_baseidx_sext_v8i32_v8f64(ptr %base, <8 x i32> %idxs
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
; RV32ZVE32F-NEXT: andi a2, a1, 1
; RV32ZVE32F-NEXT: bnez a2, .LBB94_10
@@ -11534,7 +11529,7 @@ define <8 x double> @mgather_baseidx_sext_v8i32_v8f64(ptr %base, <8 x i32> %idxs
; RV32ZVE32F-NEXT: fsd fa7, 56(a0)
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB94_10: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a2, v8
; RV32ZVE32F-NEXT: fld fa0, 0(a2)
; RV32ZVE32F-NEXT: andi a2, a1, 2
@@ -11708,7 +11703,7 @@ define <8 x double> @mgather_baseidx_zext_v8i32_v8f64(ptr %base, <8 x i32> %idxs
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
; RV32ZVE32F-NEXT: andi a2, a1, 1
; RV32ZVE32F-NEXT: bnez a2, .LBB95_10
@@ -11749,7 +11744,7 @@ define <8 x double> @mgather_baseidx_zext_v8i32_v8f64(ptr %base, <8 x i32> %idxs
; RV32ZVE32F-NEXT: fsd fa7, 56(a0)
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB95_10: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a2, v8
; RV32ZVE32F-NEXT: fld fa0, 0(a2)
; RV32ZVE32F-NEXT: andi a2, a1, 2
@@ -11946,7 +11941,7 @@ define <8 x double> @mgather_baseidx_v8f64(ptr %base, <8 x i64> %idxs, <8 x i1>
; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, a3
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
; RV32ZVE32F-NEXT: andi a2, a1, 1
; RV32ZVE32F-NEXT: bnez a2, .LBB96_10
@@ -11987,7 +11982,7 @@ define <8 x double> @mgather_baseidx_v8f64(ptr %base, <8 x i64> %idxs, <8 x i1>
; RV32ZVE32F-NEXT: fsd fa7, 56(a0)
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB96_10: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a2, v8
; RV32ZVE32F-NEXT: fld fa0, 0(a2)
; RV32ZVE32F-NEXT: andi a2, a1, 2
@@ -13056,141 +13051,141 @@ define <4 x i32> @mgather_narrow_edge_case(ptr %base) {
}
define <8 x i16> @mgather_strided_unaligned(ptr %base) {
-; RV32V-LABEL: mgather_strided_unaligned:
-; RV32V: # %bb.0:
-; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV32V-NEXT: vmset.m v8
-; RV32V-NEXT: vid.v v10
-; RV32V-NEXT: vsll.vi v10, v10, 2
-; RV32V-NEXT: vadd.vx v10, v10, a0
-; RV32V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; RV32V-NEXT: vmv.x.s a0, v8
-; RV32V-NEXT: # implicit-def: $v8
-; RV32V-NEXT: beqz zero, .LBB107_9
-; RV32V-NEXT: # %bb.1: # %else
-; RV32V-NEXT: andi a1, a0, 2
-; RV32V-NEXT: bnez a1, .LBB107_10
-; RV32V-NEXT: .LBB107_2: # %else2
-; RV32V-NEXT: andi a1, a0, 4
-; RV32V-NEXT: bnez a1, .LBB107_11
-; RV32V-NEXT: .LBB107_3: # %else5
-; RV32V-NEXT: andi a1, a0, 8
-; RV32V-NEXT: bnez a1, .LBB107_12
-; RV32V-NEXT: .LBB107_4: # %else8
-; RV32V-NEXT: andi a1, a0, 16
-; RV32V-NEXT: bnez a1, .LBB107_13
-; RV32V-NEXT: .LBB107_5: # %else11
-; RV32V-NEXT: andi a1, a0, 32
-; RV32V-NEXT: bnez a1, .LBB107_14
-; RV32V-NEXT: .LBB107_6: # %else14
-; RV32V-NEXT: andi a1, a0, 64
-; RV32V-NEXT: bnez a1, .LBB107_15
-; RV32V-NEXT: .LBB107_7: # %else17
-; RV32V-NEXT: andi a0, a0, -128
-; RV32V-NEXT: bnez a0, .LBB107_16
-; RV32V-NEXT: .LBB107_8: # %else20
-; RV32V-NEXT: ret
-; RV32V-NEXT: .LBB107_9: # %cond.load
-; RV32V-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV32V-NEXT: vmv.x.s a1, v10
-; RV32V-NEXT: lbu a2, 1(a1)
-; RV32V-NEXT: lbu a1, 0(a1)
-; RV32V-NEXT: slli a2, a2, 8
-; RV32V-NEXT: or a1, a2, a1
-; RV32V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; RV32V-NEXT: vmv.v.x v8, a1
-; RV32V-NEXT: andi a1, a0, 2
-; RV32V-NEXT: beqz a1, .LBB107_2
-; RV32V-NEXT: .LBB107_10: # %cond.load1
-; RV32V-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV32V-NEXT: vslidedown.vi v9, v10, 1
-; RV32V-NEXT: vmv.x.s a1, v9
-; RV32V-NEXT: lbu a2, 1(a1)
-; RV32V-NEXT: lbu a1, 0(a1)
-; RV32V-NEXT: slli a2, a2, 8
-; RV32V-NEXT: or a1, a2, a1
-; RV32V-NEXT: vmv.s.x v9, a1
-; RV32V-NEXT: vsetivli zero, 2, e16, m1, tu, ma
-; RV32V-NEXT: vslideup.vi v8, v9, 1
-; RV32V-NEXT: andi a1, a0, 4
-; RV32V-NEXT: beqz a1, .LBB107_3
-; RV32V-NEXT: .LBB107_11: # %cond.load4
-; RV32V-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV32V-NEXT: vslidedown.vi v9, v10, 2
-; RV32V-NEXT: vmv.x.s a1, v9
-; RV32V-NEXT: lbu a2, 1(a1)
-; RV32V-NEXT: lbu a1, 0(a1)
-; RV32V-NEXT: slli a2, a2, 8
-; RV32V-NEXT: or a1, a2, a1
-; RV32V-NEXT: vmv.s.x v9, a1
-; RV32V-NEXT: vsetivli zero, 3, e16, m1, tu, ma
-; RV32V-NEXT: vslideup.vi v8, v9, 2
-; RV32V-NEXT: andi a1, a0, 8
-; RV32V-NEXT: beqz a1, .LBB107_4
-; RV32V-NEXT: .LBB107_12: # %cond.load7
-; RV32V-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV32V-NEXT: vslidedown.vi v9, v10, 3
-; RV32V-NEXT: vmv.x.s a1, v9
-; RV32V-NEXT: lbu a2, 1(a1)
-; RV32V-NEXT: lbu a1, 0(a1)
-; RV32V-NEXT: slli a2, a2, 8
-; RV32V-NEXT: or a1, a2, a1
-; RV32V-NEXT: vmv.s.x v9, a1
-; RV32V-NEXT: vsetivli zero, 4, e16, m1, tu, ma
-; RV32V-NEXT: vslideup.vi v8, v9, 3
-; RV32V-NEXT: andi a1, a0, 16
-; RV32V-NEXT: beqz a1, .LBB107_5
-; RV32V-NEXT: .LBB107_13: # %cond.load10
-; RV32V-NEXT: vsetivli zero, 1, e32, m2, ta, ma
-; RV32V-NEXT: vslidedown.vi v12, v10, 4
-; RV32V-NEXT: vmv.x.s a1, v12
-; RV32V-NEXT: lbu a2, 1(a1)
-; RV32V-NEXT: lbu a1, 0(a1)
-; RV32V-NEXT: slli a2, a2, 8
-; RV32V-NEXT: or a1, a2, a1
-; RV32V-NEXT: vmv.s.x v9, a1
-; RV32V-NEXT: vsetivli zero, 5, e16, m1, tu, ma
-; RV32V-NEXT: vslideup.vi v8, v9, 4
-; RV32V-NEXT: andi a1, a0, 32
-; RV32V-NEXT: beqz a1, .LBB107_6
-; RV32V-NEXT: .LBB107_14: # %cond.load13
-; RV32V-NEXT: vsetivli zero, 1, e32, m2, ta, ma
-; RV32V-NEXT: vslidedown.vi v12, v10, 5
-; RV32V-NEXT: vmv.x.s a1, v12
-; RV32V-NEXT: lbu a2, 1(a1)
-; RV32V-NEXT: lbu a1, 0(a1)
-; RV32V-NEXT: slli a2, a2, 8
-; RV32V-NEXT: or a1, a2, a1
-; RV32V-NEXT: vmv.s.x v9, a1
-; RV32V-NEXT: vsetivli zero, 6, e16, m1, tu, ma
-; RV32V-NEXT: vslideup.vi v8, v9, 5
-; RV32V-NEXT: andi a1, a0, 64
-; RV32V-NEXT: beqz a1, .LBB107_7
-; RV32V-NEXT: .LBB107_15: # %cond.load16
-; RV32V-NEXT: vsetivli zero, 1, e32, m2, ta, ma
-; RV32V-NEXT: vslidedown.vi v12, v10, 6
-; RV32V-NEXT: vmv.x.s a1, v12
-; RV32V-NEXT: lbu a2, 1(a1)
-; RV32V-NEXT: lbu a1, 0(a1)
-; RV32V-NEXT: slli a2, a2, 8
-; RV32V-NEXT: or a1, a2, a1
-; RV32V-NEXT: vmv.s.x v9, a1
-; RV32V-NEXT: vsetivli zero, 7, e16, m1, tu, ma
-; RV32V-NEXT: vslideup.vi v8, v9, 6
-; RV32V-NEXT: andi a0, a0, -128
-; RV32V-NEXT: beqz a0, .LBB107_8
-; RV32V-NEXT: .LBB107_16: # %cond.load19
-; RV32V-NEXT: vsetivli zero, 1, e32, m2, ta, ma
-; RV32V-NEXT: vslidedown.vi v10, v10, 7
-; RV32V-NEXT: vmv.x.s a0, v10
-; RV32V-NEXT: lbu a1, 1(a0)
-; RV32V-NEXT: lbu a0, 0(a0)
-; RV32V-NEXT: slli a1, a1, 8
-; RV32V-NEXT: or a0, a1, a0
-; RV32V-NEXT: vmv.s.x v9, a0
-; RV32V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; RV32V-NEXT: vslideup.vi v8, v9, 7
-; RV32V-NEXT: ret
+; RV32-LABEL: mgather_strided_unaligned:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV32-NEXT: vmset.m v8
+; RV32-NEXT: vid.v v10
+; RV32-NEXT: vsll.vi v10, v10, 2
+; RV32-NEXT: vadd.vx v10, v10, a0
+; RV32-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32-NEXT: vmv.x.s a0, v8
+; RV32-NEXT: # implicit-def: $v8
+; RV32-NEXT: beqz zero, .LBB107_9
+; RV32-NEXT: # %bb.1: # %else
+; RV32-NEXT: andi a1, a0, 2
+; RV32-NEXT: bnez a1, .LBB107_10
+; RV32-NEXT: .LBB107_2: # %else2
+; RV32-NEXT: andi a1, a0, 4
+; RV32-NEXT: bnez a1, .LBB107_11
+; RV32-NEXT: .LBB107_3: # %else5
+; RV32-NEXT: andi a1, a0, 8
+; RV32-NEXT: bnez a1, .LBB107_12
+; RV32-NEXT: .LBB107_4: # %else8
+; RV32-NEXT: andi a1, a0, 16
+; RV32-NEXT: bnez a1, .LBB107_13
+; RV32-NEXT: .LBB107_5: # %else11
+; RV32-NEXT: andi a1, a0, 32
+; RV32-NEXT: bnez a1, .LBB107_14
+; RV32-NEXT: .LBB107_6: # %else14
+; RV32-NEXT: andi a1, a0, 64
+; RV32-NEXT: bnez a1, .LBB107_15
+; RV32-NEXT: .LBB107_7: # %else17
+; RV32-NEXT: andi a0, a0, -128
+; RV32-NEXT: bnez a0, .LBB107_16
+; RV32-NEXT: .LBB107_8: # %else20
+; RV32-NEXT: ret
+; RV32-NEXT: .LBB107_9: # %cond.load
+; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32-NEXT: vmv.x.s a1, v10
+; RV32-NEXT: lbu a2, 1(a1)
+; RV32-NEXT: lbu a1, 0(a1)
+; RV32-NEXT: slli a2, a2, 8
+; RV32-NEXT: or a1, a2, a1
+; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: andi a1, a0, 2
+; RV32-NEXT: beqz a1, .LBB107_2
+; RV32-NEXT: .LBB107_10: # %cond.load1
+; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV32-NEXT: vslidedown.vi v9, v10, 1
+; RV32-NEXT: vmv.x.s a1, v9
+; RV32-NEXT: lbu a2, 1(a1)
+; RV32-NEXT: lbu a1, 0(a1)
+; RV32-NEXT: slli a2, a2, 8
+; RV32-NEXT: or a1, a2, a1
+; RV32-NEXT: vmv.s.x v9, a1
+; RV32-NEXT: vsetivli zero, 2, e16, m1, tu, ma
+; RV32-NEXT: vslideup.vi v8, v9, 1
+; RV32-NEXT: andi a1, a0, 4
+; RV32-NEXT: beqz a1, .LBB107_3
+; RV32-NEXT: .LBB107_11: # %cond.load4
+; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV32-NEXT: vslidedown.vi v9, v10, 2
+; RV32-NEXT: vmv.x.s a1, v9
+; RV32-NEXT: lbu a2, 1(a1)
+; RV32-NEXT: lbu a1, 0(a1)
+; RV32-NEXT: slli a2, a2, 8
+; RV32-NEXT: or a1, a2, a1
+; RV32-NEXT: vmv.s.x v9, a1
+; RV32-NEXT: vsetivli zero, 3, e16, m1, tu, ma
+; RV32-NEXT: vslideup.vi v8, v9, 2
+; RV32-NEXT: andi a1, a0, 8
+; RV32-NEXT: beqz a1, .LBB107_4
+; RV32-NEXT: .LBB107_12: # %cond.load7
+; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV32-NEXT: vslidedown.vi v9, v10, 3
+; RV32-NEXT: vmv.x.s a1, v9
+; RV32-NEXT: lbu a2, 1(a1)
+; RV32-NEXT: lbu a1, 0(a1)
+; RV32-NEXT: slli a2, a2, 8
+; RV32-NEXT: or a1, a2, a1
+; RV32-NEXT: vmv.s.x v9, a1
+; RV32-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; RV32-NEXT: vslideup.vi v8, v9, 3
+; RV32-NEXT: andi a1, a0, 16
+; RV32-NEXT: beqz a1, .LBB107_5
+; RV32-NEXT: .LBB107_13: # %cond.load10
+; RV32-NEXT: vsetivli zero, 1, e32, m2, ta, ma
+; RV32-NEXT: vslidedown.vi v12, v10, 4
+; RV32-NEXT: vmv.x.s a1, v12
+; RV32-NEXT: lbu a2, 1(a1)
+; RV32-NEXT: lbu a1, 0(a1)
+; RV32-NEXT: slli a2, a2, 8
+; RV32-NEXT: or a1, a2, a1
+; RV32-NEXT: vmv.s.x v9, a1
+; RV32-NEXT: vsetivli zero, 5, e16, m1, tu, ma
+; RV32-NEXT: vslideup.vi v8, v9, 4
+; RV32-NEXT: andi a1, a0, 32
+; RV32-NEXT: beqz a1, .LBB107_6
+; RV32-NEXT: .LBB107_14: # %cond.load13
+; RV32-NEXT: vsetivli zero, 1, e32, m2, ta, ma
+; RV32-NEXT: vslidedown.vi v12, v10, 5
+; RV32-NEXT: vmv.x.s a1, v12
+; RV32-NEXT: lbu a2, 1(a1)
+; RV32-NEXT: lbu a1, 0(a1)
+; RV32-NEXT: slli a2, a2, 8
+; RV32-NEXT: or a1, a2, a1
+; RV32-NEXT: vmv.s.x v9, a1
+; RV32-NEXT: vsetivli zero, 6, e16, m1, tu, ma
+; RV32-NEXT: vslideup.vi v8, v9, 5
+; RV32-NEXT: andi a1, a0, 64
+; RV32-NEXT: beqz a1, .LBB107_7
+; RV32-NEXT: .LBB107_15: # %cond.load16
+; RV32-NEXT: vsetivli zero, 1, e32, m2, ta, ma
+; RV32-NEXT: vslidedown.vi v12, v10, 6
+; RV32-NEXT: vmv.x.s a1, v12
+; RV32-NEXT: lbu a2, 1(a1)
+; RV32-NEXT: lbu a1, 0(a1)
+; RV32-NEXT: slli a2, a2, 8
+; RV32-NEXT: or a1, a2, a1
+; RV32-NEXT: vmv.s.x v9, a1
+; RV32-NEXT: vsetivli zero, 7, e16, m1, tu, ma
+; RV32-NEXT: vslideup.vi v8, v9, 6
+; RV32-NEXT: andi a0, a0, -128
+; RV32-NEXT: beqz a0, .LBB107_8
+; RV32-NEXT: .LBB107_16: # %cond.load19
+; RV32-NEXT: vsetivli zero, 1, e32, m2, ta, ma
+; RV32-NEXT: vslidedown.vi v10, v10, 7
+; RV32-NEXT: vmv.x.s a0, v10
+; RV32-NEXT: lbu a1, 1(a0)
+; RV32-NEXT: lbu a0, 0(a0)
+; RV32-NEXT: slli a1, a1, 8
+; RV32-NEXT: or a0, a1, a0
+; RV32-NEXT: vmv.s.x v9, a0
+; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV32-NEXT: vslideup.vi v8, v9, 7
+; RV32-NEXT: ret
;
; RV64V-LABEL: mgather_strided_unaligned:
; RV64V: # %bb.0:
@@ -13199,7 +13194,7 @@ define <8 x i16> @mgather_strided_unaligned(ptr %base) {
; RV64V-NEXT: vid.v v12
; RV64V-NEXT: vsll.vi v12, v12, 2
; RV64V-NEXT: vadd.vx v12, v12, a0
-; RV64V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
+; RV64V-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV64V-NEXT: vmv.x.s a0, v8
; RV64V-NEXT: # implicit-def: $v8
; RV64V-NEXT: beqz zero, .LBB107_11
@@ -13263,13 +13258,13 @@ define <8 x i16> @mgather_strided_unaligned(ptr %base) {
; RV64V-NEXT: addi sp, sp, 320
; RV64V-NEXT: ret
; RV64V-NEXT: .LBB107_11: # %cond.load
-; RV64V-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV64V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV64V-NEXT: vmv.x.s a1, v12
; RV64V-NEXT: lbu a2, 1(a1)
; RV64V-NEXT: lbu a1, 0(a1)
; RV64V-NEXT: slli a2, a2, 8
; RV64V-NEXT: or a1, a2, a1
-; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; RV64V-NEXT: vmv.v.x v8, a1
; RV64V-NEXT: andi a1, a0, 2
; RV64V-NEXT: beqz a1, .LBB107_2
@@ -13344,142 +13339,6 @@ define <8 x i16> @mgather_strided_unaligned(ptr %base) {
; RV64V-NEXT: bnez a0, .LBB107_9
; RV64V-NEXT: j .LBB107_10
;
-; RV32ZVE32F-LABEL: mgather_strided_unaligned:
-; RV32ZVE32F: # %bb.0:
-; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV32ZVE32F-NEXT: vmset.m v8
-; RV32ZVE32F-NEXT: vid.v v10
-; RV32ZVE32F-NEXT: vsll.vi v10, v10, 2
-; RV32ZVE32F-NEXT: vadd.vx v10, v10, a0
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV32ZVE32F-NEXT: vmv.x.s a0, v8
-; RV32ZVE32F-NEXT: # implicit-def: $v8
-; RV32ZVE32F-NEXT: beqz zero, .LBB107_9
-; RV32ZVE32F-NEXT: # %bb.1: # %else
-; RV32ZVE32F-NEXT: andi a1, a0, 2
-; RV32ZVE32F-NEXT: bnez a1, .LBB107_10
-; RV32ZVE32F-NEXT: .LBB107_2: # %else2
-; RV32ZVE32F-NEXT: andi a1, a0, 4
-; RV32ZVE32F-NEXT: bnez a1, .LBB107_11
-; RV32ZVE32F-NEXT: .LBB107_3: # %else5
-; RV32ZVE32F-NEXT: andi a1, a0, 8
-; RV32ZVE32F-NEXT: bnez a1, .LBB107_12
-; RV32ZVE32F-NEXT: .LBB107_4: # %else8
-; RV32ZVE32F-NEXT: andi a1, a0, 16
-; RV32ZVE32F-NEXT: bnez a1, .LBB107_13
-; RV32ZVE32F-NEXT: .LBB107_5: # %else11
-; RV32ZVE32F-NEXT: andi a1, a0, 32
-; RV32ZVE32F-NEXT: bnez a1, .LBB107_14
-; RV32ZVE32F-NEXT: .LBB107_6: # %else14
-; RV32ZVE32F-NEXT: andi a1, a0, 64
-; RV32ZVE32F-NEXT: bnez a1, .LBB107_15
-; RV32ZVE32F-NEXT: .LBB107_7: # %else17
-; RV32ZVE32F-NEXT: andi a0, a0, -128
-; RV32ZVE32F-NEXT: bnez a0, .LBB107_16
-; RV32ZVE32F-NEXT: .LBB107_8: # %else20
-; RV32ZVE32F-NEXT: ret
-; RV32ZVE32F-NEXT: .LBB107_9: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV32ZVE32F-NEXT: vmv.x.s a1, v10
-; RV32ZVE32F-NEXT: lbu a2, 1(a1)
-; RV32ZVE32F-NEXT: lbu a1, 0(a1)
-; RV32ZVE32F-NEXT: slli a2, a2, 8
-; RV32ZVE32F-NEXT: or a1, a2, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; RV32ZVE32F-NEXT: vmv.v.x v8, a1
-; RV32ZVE32F-NEXT: andi a1, a0, 2
-; RV32ZVE32F-NEXT: beqz a1, .LBB107_2
-; RV32ZVE32F-NEXT: .LBB107_10: # %cond.load1
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV32ZVE32F-NEXT: vslidedown.vi v9, v10, 1
-; RV32ZVE32F-NEXT: vmv.x.s a1, v9
-; RV32ZVE32F-NEXT: lbu a2, 1(a1)
-; RV32ZVE32F-NEXT: lbu a1, 0(a1)
-; RV32ZVE32F-NEXT: slli a2, a2, 8
-; RV32ZVE32F-NEXT: or a1, a2, a1
-; RV32ZVE32F-NEXT: vmv.s.x v9, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma
-; RV32ZVE32F-NEXT: vslideup.vi v8, v9, 1
-; RV32ZVE32F-NEXT: andi a1, a0, 4
-; RV32ZVE32F-NEXT: beqz a1, .LBB107_3
-; RV32ZVE32F-NEXT: .LBB107_11: # %cond.load4
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV32ZVE32F-NEXT: vslidedown.vi v9, v10, 2
-; RV32ZVE32F-NEXT: vmv.x.s a1, v9
-; RV32ZVE32F-NEXT: lbu a2, 1(a1)
-; RV32ZVE32F-NEXT: lbu a1, 0(a1)
-; RV32ZVE32F-NEXT: slli a2, a2, 8
-; RV32ZVE32F-NEXT: or a1, a2, a1
-; RV32ZVE32F-NEXT: vmv.s.x v9, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma
-; RV32ZVE32F-NEXT: vslideup.vi v8, v9, 2
-; RV32ZVE32F-NEXT: andi a1, a0, 8
-; RV32ZVE32F-NEXT: beqz a1, .LBB107_4
-; RV32ZVE32F-NEXT: .LBB107_12: # %cond.load7
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV32ZVE32F-NEXT: vslidedown.vi v9, v10, 3
-; RV32ZVE32F-NEXT: vmv.x.s a1, v9
-; RV32ZVE32F-NEXT: lbu a2, 1(a1)
-; RV32ZVE32F-NEXT: lbu a1, 0(a1)
-; RV32ZVE32F-NEXT: slli a2, a2, 8
-; RV32ZVE32F-NEXT: or a1, a2, a1
-; RV32ZVE32F-NEXT: vmv.s.x v9, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma
-; RV32ZVE32F-NEXT: vslideup.vi v8, v9, 3
-; RV32ZVE32F-NEXT: andi a1, a0, 16
-; RV32ZVE32F-NEXT: beqz a1, .LBB107_5
-; RV32ZVE32F-NEXT: .LBB107_13: # %cond.load10
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
-; RV32ZVE32F-NEXT: vslidedown.vi v12, v10, 4
-; RV32ZVE32F-NEXT: vmv.x.s a1, v12
-; RV32ZVE32F-NEXT: lbu a2, 1(a1)
-; RV32ZVE32F-NEXT: lbu a1, 0(a1)
-; RV32ZVE32F-NEXT: slli a2, a2, 8
-; RV32ZVE32F-NEXT: or a1, a2, a1
-; RV32ZVE32F-NEXT: vmv.s.x v9, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma
-; RV32ZVE32F-NEXT: vslideup.vi v8, v9, 4
-; RV32ZVE32F-NEXT: andi a1, a0, 32
-; RV32ZVE32F-NEXT: beqz a1, .LBB107_6
-; RV32ZVE32F-NEXT: .LBB107_14: # %cond.load13
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
-; RV32ZVE32F-NEXT: vslidedown.vi v12, v10, 5
-; RV32ZVE32F-NEXT: vmv.x.s a1, v12
-; RV32ZVE32F-NEXT: lbu a2, 1(a1)
-; RV32ZVE32F-NEXT: lbu a1, 0(a1)
-; RV32ZVE32F-NEXT: slli a2, a2, 8
-; RV32ZVE32F-NEXT: or a1, a2, a1
-; RV32ZVE32F-NEXT: vmv.s.x v9, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma
-; RV32ZVE32F-NEXT: vslideup.vi v8, v9, 5
-; RV32ZVE32F-NEXT: andi a1, a0, 64
-; RV32ZVE32F-NEXT: beqz a1, .LBB107_7
-; RV32ZVE32F-NEXT: .LBB107_15: # %cond.load16
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
-; RV32ZVE32F-NEXT: vslidedown.vi v12, v10, 6
-; RV32ZVE32F-NEXT: vmv.x.s a1, v12
-; RV32ZVE32F-NEXT: lbu a2, 1(a1)
-; RV32ZVE32F-NEXT: lbu a1, 0(a1)
-; RV32ZVE32F-NEXT: slli a2, a2, 8
-; RV32ZVE32F-NEXT: or a1, a2, a1
-; RV32ZVE32F-NEXT: vmv.s.x v9, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma
-; RV32ZVE32F-NEXT: vslideup.vi v8, v9, 6
-; RV32ZVE32F-NEXT: andi a0, a0, -128
-; RV32ZVE32F-NEXT: beqz a0, .LBB107_8
-; RV32ZVE32F-NEXT: .LBB107_16: # %cond.load19
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
-; RV32ZVE32F-NEXT: vslidedown.vi v10, v10, 7
-; RV32ZVE32F-NEXT: vmv.x.s a0, v10
-; RV32ZVE32F-NEXT: lbu a1, 1(a0)
-; RV32ZVE32F-NEXT: lbu a0, 0(a0)
-; RV32ZVE32F-NEXT: slli a1, a1, 8
-; RV32ZVE32F-NEXT: or a0, a1, a0
-; RV32ZVE32F-NEXT: vmv.s.x v9, a0
-; RV32ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; RV32ZVE32F-NEXT: vslideup.vi v8, v9, 7
-; RV32ZVE32F-NEXT: ret
-;
; RV64ZVE32F-LABEL: mgather_strided_unaligned:
; RV64ZVE32F: # %bb.0:
; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
index ecc81cbaa503db4..0125c0256162c99 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
@@ -3151,7 +3151,7 @@ define void @mscatter_truemask_v4i64(<4 x i64> %val, <4 x ptr> %ptrs) {
; RV32ZVE32F-NEXT: .LBB39_5: # %cond.store
; RV32ZVE32F-NEXT: lw t0, 4(a0)
; RV32ZVE32F-NEXT: lw a0, 0(a0)
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s t1, v8
; RV32ZVE32F-NEXT: sw t0, 4(t1)
; RV32ZVE32F-NEXT: sw a0, 0(t1)
@@ -3508,7 +3508,7 @@ define void @mscatter_baseidx_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8> %id
; RV32ZVE32F-NEXT: vsext.vf4 v10, v8
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
; RV32ZVE32F-NEXT: andi s1, a1, 1
; RV32ZVE32F-NEXT: bnez s1, .LBB42_10
@@ -3548,7 +3548,7 @@ define void @mscatter_baseidx_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8> %id
; RV32ZVE32F-NEXT: .LBB42_10: # %cond.store
; RV32ZVE32F-NEXT: lw s1, 4(a0)
; RV32ZVE32F-NEXT: lw a0, 0(a0)
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s s2, v8
; RV32ZVE32F-NEXT: sw s1, 4(s2)
; RV32ZVE32F-NEXT: sw a0, 0(s2)
@@ -3752,7 +3752,7 @@ define void @mscatter_baseidx_sext_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8
; RV32ZVE32F-NEXT: vsext.vf4 v10, v8
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
; RV32ZVE32F-NEXT: andi s1, a1, 1
; RV32ZVE32F-NEXT: bnez s1, .LBB43_10
@@ -3792,7 +3792,7 @@ define void @mscatter_baseidx_sext_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8
; RV32ZVE32F-NEXT: .LBB43_10: # %cond.store
; RV32ZVE32F-NEXT: lw s1, 4(a0)
; RV32ZVE32F-NEXT: lw a0, 0(a0)
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s s2, v8
; RV32ZVE32F-NEXT: sw s1, 4(s2)
; RV32ZVE32F-NEXT: sw a0, 0(s2)
@@ -3998,7 +3998,7 @@ define void @mscatter_baseidx_zext_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8
; RV32ZVE32F-NEXT: vzext.vf4 v10, v8
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
; RV32ZVE32F-NEXT: andi s1, a1, 1
; RV32ZVE32F-NEXT: bnez s1, .LBB44_10
@@ -4038,7 +4038,7 @@ define void @mscatter_baseidx_zext_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8
; RV32ZVE32F-NEXT: .LBB44_10: # %cond.store
; RV32ZVE32F-NEXT: lw s1, 4(a0)
; RV32ZVE32F-NEXT: lw a0, 0(a0)
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s s2, v8
; RV32ZVE32F-NEXT: sw s1, 4(s2)
; RV32ZVE32F-NEXT: sw a0, 0(s2)
@@ -4251,7 +4251,7 @@ define void @mscatter_baseidx_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i16> %
; RV32ZVE32F-NEXT: vsext.vf2 v10, v8
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
; RV32ZVE32F-NEXT: andi s1, a1, 1
; RV32ZVE32F-NEXT: bnez s1, .LBB45_10
@@ -4291,7 +4291,7 @@ define void @mscatter_baseidx_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i16> %
; RV32ZVE32F-NEXT: .LBB45_10: # %cond.store
; RV32ZVE32F-NEXT: lw s1, 4(a0)
; RV32ZVE32F-NEXT: lw a0, 0(a0)
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s s2, v8
; RV32ZVE32F-NEXT: sw s1, 4(s2)
; RV32ZVE32F-NEXT: sw a0, 0(s2)
@@ -4496,7 +4496,7 @@ define void @mscatter_baseidx_sext_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV32ZVE32F-NEXT: vsext.vf2 v10, v8
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
; RV32ZVE32F-NEXT: andi s1, a1, 1
; RV32ZVE32F-NEXT: bnez s1, .LBB46_10
@@ -4536,7 +4536,7 @@ define void @mscatter_baseidx_sext_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV32ZVE32F-NEXT: .LBB46_10: # %cond.store
; RV32ZVE32F-NEXT: lw s1, 4(a0)
; RV32ZVE32F-NEXT: lw a0, 0(a0)
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s s2, v8
; RV32ZVE32F-NEXT: sw s1, 4(s2)
; RV32ZVE32F-NEXT: sw a0, 0(s2)
@@ -4743,7 +4743,7 @@ define void @mscatter_baseidx_zext_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV32ZVE32F-NEXT: vzext.vf2 v10, v8
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
; RV32ZVE32F-NEXT: andi s1, a1, 1
; RV32ZVE32F-NEXT: bnez s1, .LBB47_10
@@ -4783,7 +4783,7 @@ define void @mscatter_baseidx_zext_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV32ZVE32F-NEXT: .LBB47_10: # %cond.store
; RV32ZVE32F-NEXT: lw s1, 4(a0)
; RV32ZVE32F-NEXT: lw a0, 0(a0)
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s s2, v8
; RV32ZVE32F-NEXT: sw s1, 4(s2)
; RV32ZVE32F-NEXT: sw a0, 0(s2)
@@ -4997,7 +4997,7 @@ define void @mscatter_baseidx_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i32> %
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
; RV32ZVE32F-NEXT: andi s1, a1, 1
; RV32ZVE32F-NEXT: bnez s1, .LBB48_10
@@ -5037,7 +5037,7 @@ define void @mscatter_baseidx_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i32> %
; RV32ZVE32F-NEXT: .LBB48_10: # %cond.store
; RV32ZVE32F-NEXT: lw s1, 4(a0)
; RV32ZVE32F-NEXT: lw a0, 0(a0)
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s s2, v8
; RV32ZVE32F-NEXT: sw s1, 4(s2)
; RV32ZVE32F-NEXT: sw a0, 0(s2)
@@ -5240,7 +5240,7 @@ define void @mscatter_baseidx_sext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
; RV32ZVE32F-NEXT: andi s1, a1, 1
; RV32ZVE32F-NEXT: bnez s1, .LBB49_10
@@ -5280,7 +5280,7 @@ define void @mscatter_baseidx_sext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV32ZVE32F-NEXT: .LBB49_10: # %cond.store
; RV32ZVE32F-NEXT: lw s1, 4(a0)
; RV32ZVE32F-NEXT: lw a0, 0(a0)
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s s2, v8
; RV32ZVE32F-NEXT: sw s1, 4(s2)
; RV32ZVE32F-NEXT: sw a0, 0(s2)
@@ -5484,7 +5484,7 @@ define void @mscatter_baseidx_zext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
; RV32ZVE32F-NEXT: andi s1, a1, 1
; RV32ZVE32F-NEXT: bnez s1, .LBB50_10
@@ -5524,7 +5524,7 @@ define void @mscatter_baseidx_zext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV32ZVE32F-NEXT: .LBB50_10: # %cond.store
; RV32ZVE32F-NEXT: lw s1, 4(a0)
; RV32ZVE32F-NEXT: lw a0, 0(a0)
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s s2, v8
; RV32ZVE32F-NEXT: sw s1, 4(s2)
; RV32ZVE32F-NEXT: sw a0, 0(s2)
@@ -5763,7 +5763,7 @@ define void @mscatter_baseidx_v8i64(<8 x i64> %val, ptr %base, <8 x i64> %idxs,
; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, s2
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
; RV32ZVE32F-NEXT: andi a2, a1, 1
; RV32ZVE32F-NEXT: bnez a2, .LBB51_10
@@ -5809,7 +5809,7 @@ define void @mscatter_baseidx_v8i64(<8 x i64> %val, ptr %base, <8 x i64> %idxs,
; RV32ZVE32F-NEXT: .LBB51_10: # %cond.store
; RV32ZVE32F-NEXT: lw a2, 4(a0)
; RV32ZVE32F-NEXT: lw a0, 0(a0)
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s s2, v8
; RV32ZVE32F-NEXT: sw a2, 4(s2)
; RV32ZVE32F-NEXT: sw a0, 0(s2)
@@ -8352,7 +8352,7 @@ define void @mscatter_truemask_v4f64(<4 x double> %val, <4 x ptr> %ptrs) {
; RV32ZVE32F-NEXT: .LBB78_4: # %else6
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB78_5: # %cond.store
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v8
; RV32ZVE32F-NEXT: fsd fa0, 0(a1)
; RV32ZVE32F-NEXT: andi a1, a0, 2
@@ -8623,7 +8623,7 @@ define void @mscatter_baseidx_v8i8_v8f64(<8 x double> %val, ptr %base, <8 x i8>
; RV32ZVE32F-NEXT: vsext.vf4 v10, v8
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a0
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a0, v0
; RV32ZVE32F-NEXT: andi a1, a0, 1
; RV32ZVE32F-NEXT: bnez a1, .LBB81_9
@@ -8651,7 +8651,7 @@ define void @mscatter_baseidx_v8i8_v8f64(<8 x double> %val, ptr %base, <8 x i8>
; RV32ZVE32F-NEXT: .LBB81_8: # %else14
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB81_9: # %cond.store
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v8
; RV32ZVE32F-NEXT: fsd fa0, 0(a1)
; RV32ZVE32F-NEXT: andi a1, a0, 2
@@ -8823,7 +8823,7 @@ define void @mscatter_baseidx_sext_v8i8_v8f64(<8 x double> %val, ptr %base, <8 x
; RV32ZVE32F-NEXT: vsext.vf4 v10, v8
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a0
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a0, v0
; RV32ZVE32F-NEXT: andi a1, a0, 1
; RV32ZVE32F-NEXT: bnez a1, .LBB82_9
@@ -8851,7 +8851,7 @@ define void @mscatter_baseidx_sext_v8i8_v8f64(<8 x double> %val, ptr %base, <8 x
; RV32ZVE32F-NEXT: .LBB82_8: # %else14
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB82_9: # %cond.store
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v8
; RV32ZVE32F-NEXT: fsd fa0, 0(a1)
; RV32ZVE32F-NEXT: andi a1, a0, 2
@@ -9025,7 +9025,7 @@ define void @mscatter_baseidx_zext_v8i8_v8f64(<8 x double> %val, ptr %base, <8 x
; RV32ZVE32F-NEXT: vzext.vf4 v10, v8
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a0
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a0, v0
; RV32ZVE32F-NEXT: andi a1, a0, 1
; RV32ZVE32F-NEXT: bnez a1, .LBB83_9
@@ -9053,7 +9053,7 @@ define void @mscatter_baseidx_zext_v8i8_v8f64(<8 x double> %val, ptr %base, <8 x
; RV32ZVE32F-NEXT: .LBB83_8: # %else14
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB83_9: # %cond.store
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v8
; RV32ZVE32F-NEXT: fsd fa0, 0(a1)
; RV32ZVE32F-NEXT: andi a1, a0, 2
@@ -9234,7 +9234,7 @@ define void @mscatter_baseidx_v8i16_v8f64(<8 x double> %val, ptr %base, <8 x i16
; RV32ZVE32F-NEXT: vsext.vf2 v10, v8
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a0
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a0, v0
; RV32ZVE32F-NEXT: andi a1, a0, 1
; RV32ZVE32F-NEXT: bnez a1, .LBB84_9
@@ -9262,7 +9262,7 @@ define void @mscatter_baseidx_v8i16_v8f64(<8 x double> %val, ptr %base, <8 x i16
; RV32ZVE32F-NEXT: .LBB84_8: # %else14
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB84_9: # %cond.store
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v8
; RV32ZVE32F-NEXT: fsd fa0, 0(a1)
; RV32ZVE32F-NEXT: andi a1, a0, 2
@@ -9435,7 +9435,7 @@ define void @mscatter_baseidx_sext_v8i16_v8f64(<8 x double> %val, ptr %base, <8
; RV32ZVE32F-NEXT: vsext.vf2 v10, v8
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a0
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a0, v0
; RV32ZVE32F-NEXT: andi a1, a0, 1
; RV32ZVE32F-NEXT: bnez a1, .LBB85_9
@@ -9463,7 +9463,7 @@ define void @mscatter_baseidx_sext_v8i16_v8f64(<8 x double> %val, ptr %base, <8
; RV32ZVE32F-NEXT: .LBB85_8: # %else14
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB85_9: # %cond.store
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v8
; RV32ZVE32F-NEXT: fsd fa0, 0(a1)
; RV32ZVE32F-NEXT: andi a1, a0, 2
@@ -9638,7 +9638,7 @@ define void @mscatter_baseidx_zext_v8i16_v8f64(<8 x double> %val, ptr %base, <8
; RV32ZVE32F-NEXT: vzext.vf2 v10, v8
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a0
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a0, v0
; RV32ZVE32F-NEXT: andi a1, a0, 1
; RV32ZVE32F-NEXT: bnez a1, .LBB86_9
@@ -9666,7 +9666,7 @@ define void @mscatter_baseidx_zext_v8i16_v8f64(<8 x double> %val, ptr %base, <8
; RV32ZVE32F-NEXT: .LBB86_8: # %else14
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB86_9: # %cond.store
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v8
; RV32ZVE32F-NEXT: fsd fa0, 0(a1)
; RV32ZVE32F-NEXT: andi a1, a0, 2
@@ -9848,7 +9848,7 @@ define void @mscatter_baseidx_v8i32_v8f64(<8 x double> %val, ptr %base, <8 x i32
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a0
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a0, v0
; RV32ZVE32F-NEXT: andi a1, a0, 1
; RV32ZVE32F-NEXT: bnez a1, .LBB87_9
@@ -9876,7 +9876,7 @@ define void @mscatter_baseidx_v8i32_v8f64(<8 x double> %val, ptr %base, <8 x i32
; RV32ZVE32F-NEXT: .LBB87_8: # %else14
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB87_9: # %cond.store
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v8
; RV32ZVE32F-NEXT: fsd fa0, 0(a1)
; RV32ZVE32F-NEXT: andi a1, a0, 2
@@ -10047,7 +10047,7 @@ define void @mscatter_baseidx_sext_v8i32_v8f64(<8 x double> %val, ptr %base, <8
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a0
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a0, v0
; RV32ZVE32F-NEXT: andi a1, a0, 1
; RV32ZVE32F-NEXT: bnez a1, .LBB88_9
@@ -10075,7 +10075,7 @@ define void @mscatter_baseidx_sext_v8i32_v8f64(<8 x double> %val, ptr %base, <8
; RV32ZVE32F-NEXT: .LBB88_8: # %else14
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB88_9: # %cond.store
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v8
; RV32ZVE32F-NEXT: fsd fa0, 0(a1)
; RV32ZVE32F-NEXT: andi a1, a0, 2
@@ -10247,7 +10247,7 @@ define void @mscatter_baseidx_zext_v8i32_v8f64(<8 x double> %val, ptr %base, <8
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a0
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a0, v0
; RV32ZVE32F-NEXT: andi a1, a0, 1
; RV32ZVE32F-NEXT: bnez a1, .LBB89_9
@@ -10275,7 +10275,7 @@ define void @mscatter_baseidx_zext_v8i32_v8f64(<8 x double> %val, ptr %base, <8
; RV32ZVE32F-NEXT: .LBB89_8: # %else14
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB89_9: # %cond.store
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v8
; RV32ZVE32F-NEXT: fsd fa0, 0(a1)
; RV32ZVE32F-NEXT: andi a1, a0, 2
@@ -10470,7 +10470,7 @@ define void @mscatter_baseidx_v8f64(<8 x double> %val, ptr %base, <8 x i64> %idx
; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, a2
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a0
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a0, v0
; RV32ZVE32F-NEXT: andi a1, a0, 1
; RV32ZVE32F-NEXT: bnez a1, .LBB90_9
@@ -10498,7 +10498,7 @@ define void @mscatter_baseidx_v8f64(<8 x double> %val, ptr %base, <8 x i64> %idx
; RV32ZVE32F-NEXT: .LBB90_8: # %else14
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB90_9: # %cond.store
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v8
; RV32ZVE32F-NEXT: fsd fa0, 0(a1)
; RV32ZVE32F-NEXT: andi a1, a0, 2
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
index 3f6aa72bc2e3b2b..b212e1ce9988615 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
@@ -306,7 +306,7 @@ define float @vreduce_ord_fwadd_v1f32(ptr %x, float %s) {
; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfwredosum.vs v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <1 x half>, ptr %x
@@ -353,7 +353,7 @@ define float @vreduce_fwadd_v2f32(ptr %x, float %s) {
; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfwredusum.vs v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <2 x half>, ptr %x
@@ -370,7 +370,7 @@ define float @vreduce_ord_fwadd_v2f32(ptr %x, float %s) {
; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfwredosum.vs v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <2 x half>, ptr %x
@@ -481,7 +481,7 @@ define float @vreduce_fwadd_v8f32(ptr %x, float %s) {
; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfwredusum.vs v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <8 x half>, ptr %x
@@ -498,7 +498,7 @@ define float @vreduce_ord_fwadd_v8f32(ptr %x, float %s) {
; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfwredosum.vs v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <8 x half>, ptr %x
@@ -545,7 +545,7 @@ define float @vreduce_fwadd_v16f32(ptr %x, float %s) {
; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vfwredusum.vs v8, v8, v10
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <16 x half>, ptr %x
@@ -562,7 +562,7 @@ define float @vreduce_ord_fwadd_v16f32(ptr %x, float %s) {
; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vfwredosum.vs v8, v8, v10
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <16 x half>, ptr %x
@@ -612,7 +612,7 @@ define float @vreduce_fwadd_v32f32(ptr %x, float %s) {
; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfwredusum.vs v8, v8, v12
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <32 x half>, ptr %x
@@ -630,7 +630,7 @@ define float @vreduce_ord_fwadd_v32f32(ptr %x, float %s) {
; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfwredosum.vs v8, v8, v12
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <32 x half>, ptr %x
@@ -708,12 +708,12 @@ define float @vreduce_ord_fwadd_v64f32(ptr %x, float %s) {
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vslidedown.vx v16, v8, a0
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; CHECK-NEXT: vfmv.s.f v12, fa0
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfwredosum.vs v8, v8, v12
; CHECK-NEXT: vfwredosum.vs v8, v16, v8
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <64 x half>, ptr %x
@@ -886,7 +886,7 @@ define double @vreduce_fwadd_v4f64(ptr %x, double %s) {
; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfwredusum.vs v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <4 x float>, ptr %x
@@ -903,7 +903,7 @@ define double @vreduce_ord_fwadd_v4f64(ptr %x, double %s) {
; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfwredosum.vs v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <4 x float>, ptr %x
@@ -950,7 +950,7 @@ define double @vreduce_fwadd_v8f64(ptr %x, double %s) {
; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfwredusum.vs v8, v8, v10
-; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <8 x float>, ptr %x
@@ -967,7 +967,7 @@ define double @vreduce_ord_fwadd_v8f64(ptr %x, double %s) {
; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfwredosum.vs v8, v8, v10
-; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <8 x float>, ptr %x
@@ -1014,7 +1014,7 @@ define double @vreduce_fwadd_v16f64(ptr %x, double %s) {
; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfwredusum.vs v8, v8, v12
-; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <16 x float>, ptr %x
@@ -1031,7 +1031,7 @@ define double @vreduce_ord_fwadd_v16f64(ptr %x, double %s) {
; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfwredosum.vs v8, v8, v12
-; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <16 x float>, ptr %x
@@ -1105,12 +1105,12 @@ define double @vreduce_ord_fwadd_v32f64(ptr %x, double %s) {
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v16, v8, 16
-; CHECK-NEXT: vsetivli zero, 16, e64, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vfmv.s.f v12, fa0
-; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfwredosum.vs v8, v8, v12
; CHECK-NEXT: vfwredosum.vs v8, v16, v8
-; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <32 x float>, ptr %x
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
index 90ded1d70d5fc17..6c75c9b9c294982 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
@@ -217,7 +217,7 @@ define i16 @vwreduce_add_v2i16(ptr %x) {
; CHECK-NEXT: vmv.s.x v9, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT: vwredsum.vs v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <2 x i8>, ptr %x
@@ -234,7 +234,7 @@ define i16 @vwreduce_uadd_v2i16(ptr %x) {
; CHECK-NEXT: vmv.s.x v9, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT: vwredsumu.vs v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <2 x i8>, ptr %x
@@ -267,7 +267,7 @@ define i16 @vwreduce_add_v4i16(ptr %x) {
; CHECK-NEXT: vmv.s.x v9, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT: vwredsum.vs v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <4 x i8>, ptr %x
@@ -284,7 +284,7 @@ define i16 @vwreduce_uadd_v4i16(ptr %x) {
; CHECK-NEXT: vmv.s.x v9, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT: vwredsumu.vs v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <4 x i8>, ptr %x
@@ -367,7 +367,7 @@ define i16 @vwreduce_add_v16i16(ptr %x) {
; CHECK-NEXT: vmv.s.x v9, zero
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; CHECK-NEXT: vwredsum.vs v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <16 x i8>, ptr %x
@@ -384,7 +384,7 @@ define i16 @vwreduce_uadd_v16i16(ptr %x) {
; CHECK-NEXT: vmv.s.x v9, zero
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; CHECK-NEXT: vwredsumu.vs v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <16 x i8>, ptr %x
@@ -419,7 +419,7 @@ define i16 @vwreduce_add_v32i16(ptr %x) {
; CHECK-NEXT: vmv.s.x v10, zero
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
; CHECK-NEXT: vwredsum.vs v8, v8, v10
-; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <32 x i8>, ptr %x
@@ -437,7 +437,7 @@ define i16 @vwreduce_uadd_v32i16(ptr %x) {
; CHECK-NEXT: vmv.s.x v10, zero
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
; CHECK-NEXT: vwredsumu.vs v8, v8, v10
-; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <32 x i8>, ptr %x
@@ -472,7 +472,7 @@ define i16 @vwreduce_add_v64i16(ptr %x) {
; CHECK-NEXT: vmv.s.x v12, zero
; CHECK-NEXT: vsetvli zero, zero, e8, m4, ta, ma
; CHECK-NEXT: vwredsum.vs v8, v8, v12
-; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <64 x i8>, ptr %x
@@ -490,7 +490,7 @@ define i16 @vwreduce_uadd_v64i16(ptr %x) {
; CHECK-NEXT: vmv.s.x v12, zero
; CHECK-NEXT: vsetvli zero, zero, e8, m4, ta, ma
; CHECK-NEXT: vwredsumu.vs v8, v8, v12
-; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <64 x i8>, ptr %x
@@ -629,7 +629,7 @@ define i32 @vwreduce_add_v2i32(ptr %x) {
; CHECK-NEXT: vmv.s.x v9, zero
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vwredsum.vs v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <2 x i16>, ptr %x
@@ -646,7 +646,7 @@ define i32 @vwreduce_uadd_v2i32(ptr %x) {
; CHECK-NEXT: vmv.s.x v9, zero
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vwredsumu.vs v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <2 x i16>, ptr %x
@@ -729,7 +729,7 @@ define i32 @vwreduce_add_v8i32(ptr %x) {
; CHECK-NEXT: vmv.s.x v9, zero
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vwredsum.vs v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <8 x i16>, ptr %x
@@ -746,7 +746,7 @@ define i32 @vwreduce_uadd_v8i32(ptr %x) {
; CHECK-NEXT: vmv.s.x v9, zero
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vwredsumu.vs v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <8 x i16>, ptr %x
@@ -779,7 +779,7 @@ define i32 @vwreduce_add_v16i32(ptr %x) {
; CHECK-NEXT: vmv.s.x v10, zero
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vwredsum.vs v8, v8, v10
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <16 x i16>, ptr %x
@@ -796,7 +796,7 @@ define i32 @vwreduce_uadd_v16i32(ptr %x) {
; CHECK-NEXT: vmv.s.x v10, zero
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vwredsumu.vs v8, v8, v10
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <16 x i16>, ptr %x
@@ -831,7 +831,7 @@ define i32 @vwreduce_add_v32i32(ptr %x) {
; CHECK-NEXT: vmv.s.x v12, zero
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vwredsum.vs v8, v8, v12
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <32 x i16>, ptr %x
@@ -849,7 +849,7 @@ define i32 @vwreduce_uadd_v32i32(ptr %x) {
; CHECK-NEXT: vmv.s.x v12, zero
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vwredsumu.vs v8, v8, v12
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <32 x i16>, ptr %x
@@ -1138,7 +1138,7 @@ define i64 @vwreduce_add_v4i64(ptr %x) {
; RV64-NEXT: vmv.s.x v9, zero
; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; RV64-NEXT: vwredsum.vs v8, v8, v9
-; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <4 x i32>, ptr %x
@@ -1169,7 +1169,7 @@ define i64 @vwreduce_uadd_v4i64(ptr %x) {
; RV64-NEXT: vmv.s.x v9, zero
; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; RV64-NEXT: vwredsumu.vs v8, v8, v9
-; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <4 x i32>, ptr %x
@@ -1229,7 +1229,7 @@ define i64 @vwreduce_add_v8i64(ptr %x) {
; RV64-NEXT: vmv.s.x v10, zero
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV64-NEXT: vwredsum.vs v8, v8, v10
-; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <8 x i32>, ptr %x
@@ -1260,7 +1260,7 @@ define i64 @vwreduce_uadd_v8i64(ptr %x) {
; RV64-NEXT: vmv.s.x v10, zero
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV64-NEXT: vwredsumu.vs v8, v8, v10
-; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <8 x i32>, ptr %x
@@ -1320,7 +1320,7 @@ define i64 @vwreduce_add_v16i64(ptr %x) {
; RV64-NEXT: vmv.s.x v12, zero
; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; RV64-NEXT: vwredsum.vs v8, v8, v12
-; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <16 x i32>, ptr %x
@@ -1351,7 +1351,7 @@ define i64 @vwreduce_uadd_v16i64(ptr %x) {
; RV64-NEXT: vmv.s.x v12, zero
; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; RV64-NEXT: vwredsumu.vs v8, v8, v12
-; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <16 x i32>, ptr %x
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
index 1cc09b7f5eeb5f4..42be2675e1d90f1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
@@ -278,9 +278,9 @@ define void @mscatter_v4i16_align1(<4 x i16> %val, <4 x ptr> %ptrs, <4 x i1> %m)
; RV32-SLOW-NEXT: .LBB6_4: # %else6
; RV32-SLOW-NEXT: ret
; RV32-SLOW-NEXT: .LBB6_5: # %cond.store
-; RV32-SLOW-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV32-SLOW-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; RV32-SLOW-NEXT: vmv.x.s a1, v8
-; RV32-SLOW-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32-SLOW-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; RV32-SLOW-NEXT: vmv.x.s a2, v9
; RV32-SLOW-NEXT: sb a1, 0(a2)
; RV32-SLOW-NEXT: srli a1, a1, 8
@@ -341,9 +341,9 @@ define void @mscatter_v4i16_align1(<4 x i16> %val, <4 x ptr> %ptrs, <4 x i1> %m)
; RV64-SLOW-NEXT: .LBB6_4: # %else6
; RV64-SLOW-NEXT: ret
; RV64-SLOW-NEXT: .LBB6_5: # %cond.store
-; RV64-SLOW-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64-SLOW-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; RV64-SLOW-NEXT: vmv.x.s a1, v8
-; RV64-SLOW-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; RV64-SLOW-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64-SLOW-NEXT: vmv.x.s a2, v10
; RV64-SLOW-NEXT: srli a3, a1, 8
; RV64-SLOW-NEXT: sb a3, 1(a2)
@@ -506,7 +506,7 @@ define void @masked_load_v2i32_align1(ptr %a, <2 x i32> %m, ptr %res_ptr) nounwi
; RV32-SLOW-NEXT: slli a6, a6, 24
; RV32-SLOW-NEXT: or a4, a6, a5
; RV32-SLOW-NEXT: or a3, a4, a3
-; RV32-SLOW-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; RV32-SLOW-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; RV32-SLOW-NEXT: vmv.v.x v8, a3
; RV32-SLOW-NEXT: .LBB8_2: # %else
; RV32-SLOW-NEXT: andi a2, a2, 2
@@ -522,11 +522,11 @@ define void @masked_load_v2i32_align1(ptr %a, <2 x i32> %m, ptr %res_ptr) nounwi
; RV32-SLOW-NEXT: slli a0, a0, 24
; RV32-SLOW-NEXT: or a0, a0, a4
; RV32-SLOW-NEXT: or a0, a0, a2
-; RV32-SLOW-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; RV32-SLOW-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; RV32-SLOW-NEXT: vmv.s.x v9, a0
; RV32-SLOW-NEXT: vslideup.vi v8, v9, 1
; RV32-SLOW-NEXT: .LBB8_4: # %else2
-; RV32-SLOW-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; RV32-SLOW-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; RV32-SLOW-NEXT: vse32.v v8, (a1)
; RV32-SLOW-NEXT: ret
;
@@ -550,7 +550,7 @@ define void @masked_load_v2i32_align1(ptr %a, <2 x i32> %m, ptr %res_ptr) nounwi
; RV64-SLOW-NEXT: slli a6, a6, 24
; RV64-SLOW-NEXT: or a4, a6, a5
; RV64-SLOW-NEXT: or a3, a4, a3
-; RV64-SLOW-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; RV64-SLOW-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; RV64-SLOW-NEXT: vmv.v.x v8, a3
; RV64-SLOW-NEXT: .LBB8_2: # %else
; RV64-SLOW-NEXT: andi a2, a2, 2
@@ -566,11 +566,11 @@ define void @masked_load_v2i32_align1(ptr %a, <2 x i32> %m, ptr %res_ptr) nounwi
; RV64-SLOW-NEXT: slli a0, a0, 24
; RV64-SLOW-NEXT: or a0, a0, a4
; RV64-SLOW-NEXT: or a0, a0, a2
-; RV64-SLOW-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; RV64-SLOW-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; RV64-SLOW-NEXT: vmv.s.x v9, a0
; RV64-SLOW-NEXT: vslideup.vi v8, v9, 1
; RV64-SLOW-NEXT: .LBB8_4: # %else2
-; RV64-SLOW-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; RV64-SLOW-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; RV64-SLOW-NEXT: vse32.v v8, (a1)
; RV64-SLOW-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
index c5245451dc44091..2546ec95a007939 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
@@ -115,7 +115,7 @@ define float @vreduce_fwadd_nxv1f32(<vscale x 1 x half> %v, float %s) {
; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfwredusum.vs v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%e = fpext <vscale x 1 x half> %v to <vscale x 1 x float>
@@ -130,7 +130,7 @@ define float @vreduce_ord_fwadd_nxv1f32(<vscale x 1 x half> %v, float %s) {
; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfwredosum.vs v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%e = fpext <vscale x 1 x half> %v to <vscale x 1 x float>
@@ -227,7 +227,7 @@ define float @vreduce_fwadd_nxv4f32(<vscale x 4 x half> %v, float %s) {
; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vfwredusum.vs v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%e = fpext <vscale x 4 x half> %v to <vscale x 4 x float>
@@ -242,7 +242,7 @@ define float @vreduce_ord_fwadd_nxv4f32(<vscale x 4 x half> %v, float %s) {
; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vfwredosum.vs v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%e = fpext <vscale x 4 x half> %v to <vscale x 4 x float>
@@ -339,7 +339,7 @@ define double @vreduce_fwadd_nxv2f64(<vscale x 2 x float> %v, double %s) {
; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vfwredusum.vs v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%e = fpext <vscale x 2 x float> %v to <vscale x 2 x double>
@@ -354,7 +354,7 @@ define double @vreduce_ord_fwadd_nxv2f64(<vscale x 2 x float> %v, double %s) {
; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vfwredosum.vs v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%e = fpext <vscale x 2 x float> %v to <vscale x 2 x double>
@@ -395,7 +395,7 @@ define double @vreduce_fwadd_nxv4f64(<vscale x 4 x float> %v, double %s) {
; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vfwredusum.vs v8, v8, v10
-; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%e = fpext <vscale x 4 x float> %v to <vscale x 4 x double>
@@ -410,7 +410,7 @@ define double @vreduce_ord_fwadd_nxv4f64(<vscale x 4 x float> %v, double %s) {
; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vfwredosum.vs v8, v8, v10
-; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%e = fpext <vscale x 4 x float> %v to <vscale x 4 x double>
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
index 9f7b64c79616e5a..290fb6daedd0c8e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
@@ -1700,7 +1700,7 @@ define signext i64 @vwpreduce_add_nxv2i32(i64 signext %s, <vscale x 2 x i32> %v,
; RV64-NEXT: vmv.s.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e32, m1, ta, ma
; RV64-NEXT: vwredsum.vs v9, v8, v9, v0.t
-; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%e = sext <vscale x 2 x i32> %v to <vscale x 2 x i64>
@@ -1734,7 +1734,7 @@ define signext i64 @vwpreduce_uadd_nxv2i32(i64 signext %s, <vscale x 2 x i32> %v
; RV64-NEXT: vmv.s.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e32, m1, ta, ma
; RV64-NEXT: vwredsum.vs v9, v8, v9, v0.t
-; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%e = sext <vscale x 2 x i32> %v to <vscale x 2 x i64>
@@ -2040,7 +2040,7 @@ define signext i64 @vpwreduce_add_nxv4i32(i64 signext %s, <vscale x 4 x i32> %v,
; RV64-NEXT: vmv.s.x v10, a0
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, ma
; RV64-NEXT: vwredsum.vs v10, v8, v10, v0.t
-; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV64-NEXT: vmv.x.s a0, v10
; RV64-NEXT: ret
%e = sext <vscale x 4 x i32> %v to <vscale x 4 x i64>
@@ -2074,7 +2074,7 @@ define signext i64 @vpwreduce_uadd_nxv4i32(i64 signext %s, <vscale x 4 x i32> %v
; RV64-NEXT: vmv.s.x v10, a0
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, ma
; RV64-NEXT: vwredsumu.vs v10, v8, v10, v0.t
-; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV64-NEXT: vmv.x.s a0, v10
; RV64-NEXT: ret
%e = zext <vscale x 4 x i32> %v to <vscale x 4 x i64>
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
index 3f1892ede5678c0..6e24d58f9695657 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
@@ -343,7 +343,7 @@ define signext i16 @vwreduce_add_nxv1i8(<vscale x 1 x i8> %v) {
; CHECK-NEXT: vmv.s.x v9, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT: vwredsum.vs v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%e = sext <vscale x 1 x i8> %v to <vscale x 1 x i16>
@@ -358,7 +358,7 @@ define signext i16 @vwreduce_uadd_nxv1i8(<vscale x 1 x i8> %v) {
; CHECK-NEXT: vmv.s.x v9, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT: vwredsum.vs v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%e = sext <vscale x 1 x i8> %v to <vscale x 1 x i16>
@@ -479,7 +479,7 @@ define signext i16 @vwreduce_add_nxv2i8(<vscale x 2 x i8> %v) {
; CHECK-NEXT: vmv.s.x v9, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT: vwredsum.vs v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%e = sext <vscale x 2 x i8> %v to <vscale x 2 x i16>
@@ -494,7 +494,7 @@ define signext i16 @vwreduce_uadd_nxv2i8(<vscale x 2 x i8> %v) {
; CHECK-NEXT: vmv.s.x v9, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT: vwredsum.vs v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%e = sext <vscale x 2 x i8> %v to <vscale x 2 x i16>
@@ -751,7 +751,7 @@ define signext i32 @vwreduce_add_nxv1i16(<vscale x 1 x i16> %v) {
; CHECK-NEXT: vmv.s.x v9, zero
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vwredsum.vs v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%e = sext <vscale x 1 x i16> %v to <vscale x 1 x i32>
@@ -766,7 +766,7 @@ define signext i32 @vwreduce_uadd_nxv1i16(<vscale x 1 x i16> %v) {
; CHECK-NEXT: vmv.s.x v9, zero
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vwredsumu.vs v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%e = zext <vscale x 1 x i16> %v to <vscale x 1 x i32>
@@ -1023,7 +1023,7 @@ define signext i32 @vwreduce_add_nxv4i16(<vscale x 4 x i16> %v) {
; CHECK-NEXT: vmv.s.x v9, zero
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vwredsum.vs v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%e = sext <vscale x 4 x i16> %v to <vscale x 4 x i32>
@@ -1038,7 +1038,7 @@ define signext i32 @vwreduce_uadd_nxv4i16(<vscale x 4 x i16> %v) {
; CHECK-NEXT: vmv.s.x v9, zero
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vwredsumu.vs v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%e = zext <vscale x 4 x i16> %v to <vscale x 4 x i32>
@@ -1436,7 +1436,7 @@ define i64 @vwreduce_add_nxv2i32(<vscale x 2 x i32> %v) {
; RV64-NEXT: vmv.s.x v9, zero
; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; RV64-NEXT: vwredsum.vs v8, v8, v9
-; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%e = sext <vscale x 2 x i32> %v to <vscale x 2 x i64>
@@ -1464,7 +1464,7 @@ define i64 @vwreduce_uadd_nxv2i32(<vscale x 2 x i32> %v) {
; RV64-NEXT: vmv.s.x v9, zero
; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; RV64-NEXT: vwredsumu.vs v8, v8, v9
-; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%e = zext <vscale x 2 x i32> %v to <vscale x 2 x i64>
@@ -1688,7 +1688,7 @@ define i64 @vwreduce_add_nxv4i32(<vscale x 4 x i32> %v) {
; RV64-NEXT: vmv.s.x v10, zero
; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; RV64-NEXT: vwredsum.vs v8, v8, v10
-; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%e = sext <vscale x 4 x i32> %v to <vscale x 4 x i64>
@@ -1716,7 +1716,7 @@ define i64 @vwreduce_uadd_nxv4i32(<vscale x 4 x i32> %v) {
; RV64-NEXT: vmv.s.x v10, zero
; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; RV64-NEXT: vwredsumu.vs v8, v8, v10
-; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%e = zext <vscale x 4 x i32> %v to <vscale x 4 x i64>
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
index 73f651225da64d3..2e2f6354376f9d1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
@@ -896,7 +896,7 @@ define <vscale x 2 x i32> @test_ratio_only_vmv_s_x(<vscale x 2 x i32>* %x, <vsca
; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: .LBB20_3: # %if.end
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, tu, ma
; CHECK-NEXT: vmv.s.x v8, zero
; CHECK-NEXT: ret
entry:
@@ -928,7 +928,7 @@ define <vscale x 2 x i32> @test_ratio_only_vmv_s_x2(<vscale x 2 x i32>* %x, <vsc
; CHECK-NEXT: vle16.v v9, (a1)
; CHECK-NEXT: vwcvt.x.x.v v8, v9
; CHECK-NEXT: .LBB21_3: # %if.end
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, tu, ma
; CHECK-NEXT: vmv.s.x v8, zero
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
index 4d0f640408dd2a9..1114c7657c63d34 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
@@ -329,9 +329,8 @@ entry:
define double @test17(i64 %avl, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
; CHECK-LABEL: test17:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli a0, a0, e64, m1, ta, ma
-; CHECK-NEXT: vfmv.f.s fa5, v8
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT: vfmv.f.s fa5, v8
; CHECK-NEXT: vfadd.vv v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa4, v8
; CHECK-NEXT: fadd.d fa0, fa5, fa4
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll
index 22eb2d8fb99a15e..bb49b9fd65d0ff9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll
@@ -12,7 +12,7 @@ define i32 @illegal_preserve_vl(<vscale x 2 x i32> %a, <vscale x 4 x i64> %x, <v
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; CHECK-NEXT: vadd.vv v12, v12, v12
; CHECK-NEXT: vs4r.v v12, (a0)
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%index = add <vscale x 4 x i64> %x, %x
>From b227978cd8bfef4d096b6686065d11e76a482080 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Wed, 15 Nov 2023 15:48:35 +0800
Subject: [PATCH 2/3] Update test outside of rvv directory
---
llvm/test/CodeGen/RISCV/double_reduct.ll | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/RISCV/double_reduct.ll b/llvm/test/CodeGen/RISCV/double_reduct.ll
index 92f78032e81bfc3..25228b21ef0554d 100644
--- a/llvm/test/CodeGen/RISCV/double_reduct.ll
+++ b/llvm/test/CodeGen/RISCV/double_reduct.ll
@@ -113,7 +113,7 @@ define i16 @add_ext_v32i16(<32 x i8> %a, <16 x i8> %b) {
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vwredsumu.vs v8, v8, v10
-; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%ae = zext <32 x i8> %a to <32 x i16>
>From 9d9fcf6ae391546a74b863b6b344f3ee52ffc56c Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Mon, 20 Nov 2023 13:59:42 +0800
Subject: [PATCH 3/3] Try to reduce code diff
---
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 18 ++++++++----------
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index 8483b770353a84f..18fc860e4060335 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -1032,26 +1032,24 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
if (Info.hasSEWLMULRatioOnly() || !Info.isValid() || Info.isUnknown())
Info = NewInfo;
- DemandedFields Demanded = getDemanded(MI, MRI, ST);
-
// If we don't use LMUL or the SEW/LMUL ratio, then adjust LMUL so that we
// maintain the SEW/LMUL ratio. This allows us to eliminate VL toggles in more
// places.
+ DemandedFields Demanded = getDemanded(MI, MRI, ST);
if (!Demanded.LMUL && !Demanded.SEWLMULRatio && Info.isValid() &&
!Info.isUnknown()) {
- if (auto SameRatioLMUL = RISCVVType::getSameRatioLMUL(
+ if (auto NewVLMul = RISCVVType::getSameRatioLMUL(
Info.getSEW(), Info.getVLMUL(), NewInfo.getSEW())) {
- NewInfo.setVLMul(*SameRatioLMUL);
+ NewInfo.setVLMul(*NewVLMul);
Demanded.LMUL = true;
}
}
- // If AVL is defined by a vsetvli with the same VLMAX, we can replace the AVL
- // operand with the AVL of the defining vsetvli. We avoid general register
- // AVLs to avoid extending live ranges without being sure we can kill the
- // original source reg entirely.
- if (RISCVII::hasVLOp(TSFlags) && NewInfo.hasAVLReg() &&
- NewInfo.getAVLReg().isVirtual()) {
+ // If AVL is defined by a vsetvli with the same VLMAX, we can
+ // replace the AVL operand with the AVL of the defining vsetvli.
+ // We avoid general register AVLs to avoid extending live ranges
+ // without being sure we can kill the original source reg entirely.
+ if (NewInfo.hasAVLReg() && NewInfo.getAVLReg().isVirtual()) {
MachineInstr *DefMI = MRI->getVRegDef(NewInfo.getAVLReg());
if (DefMI && isVectorConfigInstr(*DefMI)) {
VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
More information about the llvm-commits
mailing list