[llvm] 160a13a - [X86] Add more tests for transform `(icmp eq/ne (and X,C0),(shift X,C1))`; PR71598
Noah Goldstein via llvm-commits
llvm-commits at lists.llvm.org
Sun Nov 19 10:15:26 PST 2023
Author: Noah Goldstein
Date: 2023-11-19T12:15:03-06:00
New Revision: 160a13a0cc98afc15c08bdeb07bec8f72b04e051
URL: https://github.com/llvm/llvm-project/commit/160a13a0cc98afc15c08bdeb07bec8f72b04e051
DIFF: https://github.com/llvm/llvm-project/commit/160a13a0cc98afc15c08bdeb07bec8f72b04e051.diff
LOG: [X86] Add more tests for transform `(icmp eq/ne (and X,C0),(shift X,C1))`; PR71598
Added:
Modified:
llvm/test/CodeGen/X86/cmp-shiftX-maskX.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/cmp-shiftX-maskX.ll b/llvm/test/CodeGen/X86/cmp-shiftX-maskX.ll
index 8ec142acb71d4ce..063f8c606624dde 100644
--- a/llvm/test/CodeGen/X86/cmp-shiftX-maskX.ll
+++ b/llvm/test/CodeGen/X86/cmp-shiftX-maskX.ll
@@ -570,6 +570,231 @@ define <16 x i1> @shl_to_ror_eq_16xi16_s8_fail_preserve_i16(<16 x i16> %x) {
ret <16 x i1> %r
}
+define i1 @shr_to_shl_eq_i32_s5_fail_doesnt_add_up(i32 %x) {
+; CHECK-LABEL: shr_to_shl_eq_i32_s5_fail_doesnt_add_up:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: andl $7, %eax
+; CHECK-NEXT: shrl $5, %edi
+; CHECK-NEXT: cmpl %edi, %eax
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: retq
+ %and = and i32 %x, 7
+ %sh = lshr i32 %x, 5
+ %r = icmp eq i32 %and, %sh
+ ret i1 %r
+}
+
+define i1 @shr_to_shl_eq_i8_s5_fail_doesnt_add_up2(i32 %x) {
+; CHECK-LABEL: shr_to_shl_eq_i8_s5_fail_doesnt_add_up2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: andl $268435455, %eax # imm = 0xFFFFFFF
+; CHECK-NEXT: shrl $5, %edi
+; CHECK-NEXT: cmpl %edi, %eax
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: retq
+ %and = and i32 %x, 268435455
+ %sh = lshr i32 %x, 5
+ %r = icmp eq i32 %and, %sh
+ ret i1 %r
+}
+
+define i1 @shr_to_shl_eq_i8_s5_fail_doesnt_add_up3(i32 %x) {
+; CHECK-LABEL: shr_to_shl_eq_i8_s5_fail_doesnt_add_up3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: andl $67108863, %eax # imm = 0x3FFFFFF
+; CHECK-NEXT: shrl $5, %edi
+; CHECK-NEXT: cmpl %edi, %eax
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: retq
+ %and = and i32 %x, 67108863
+ %sh = lshr i32 %x, 5
+ %r = icmp eq i32 %and, %sh
+ ret i1 %r
+}
+
+define i1 @shr_to_shl_eq_i8_s5_fail_doesnt_not_mask(i32 %x) {
+; CHECK-LABEL: shr_to_shl_eq_i8_s5_fail_doesnt_not_mask:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: andl $11, %eax
+; CHECK-NEXT: shrl $5, %edi
+; CHECK-NEXT: cmpl %edi, %eax
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: retq
+ %and = and i32 %x, 11
+ %sh = lshr i32 %x, 5
+ %r = icmp eq i32 %and, %sh
+ ret i1 %r
+}
+
+define i1 @shl_to_shr_eq_i32_s9_fail_wrong_mask(i32 %x) {
+; CHECK-LABEL: shl_to_shr_eq_i32_s9_fail_wrong_mask:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: andl $511, %eax # imm = 0x1FF
+; CHECK-NEXT: shll $9, %edi
+; CHECK-NEXT: cmpl %edi, %eax
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: retq
+ %and = and i32 %x, 511
+ %sh = shl i32 %x, 9
+ %r = icmp eq i32 %and, %sh
+ ret i1 %r
+}
+
+define i1 @shr_to_shl_eq_i32_s5_fail_wrong_mask(i32 %x) {
+; CHECK-LABEL: shr_to_shl_eq_i32_s5_fail_wrong_mask:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: andl $-32, %eax
+; CHECK-NEXT: shrl $5, %edi
+; CHECK-NEXT: cmpl %edi, %eax
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: retq
+ %and = and i32 %x, -32
+ %sh = lshr i32 %x, 5
+ %r = icmp eq i32 %and, %sh
+ ret i1 %r
+}
+
+define i1 @shl_to_shr_eq_i32_s9_fail_doesnt_add_up(i32 %x) {
+; CHECK-LABEL: shl_to_shr_eq_i32_s9_fail_doesnt_add_up:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: andl $65024, %eax # imm = 0xFE00
+; CHECK-NEXT: shll $9, %edi
+; CHECK-NEXT: cmpl %edi, %eax
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: retq
+ %and = and i32 %x, 65024
+ %sh = shl i32 %x, 9
+ %r = icmp eq i32 %and, %sh
+ ret i1 %r
+}
+
+define i1 @shl_to_shr_eq_i32_s9_fail_doesnt_add_up2(i32 %x) {
+; CHECK-LABEL: shl_to_shr_eq_i32_s9_fail_doesnt_add_up2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: andl $-1024, %eax # imm = 0xFC00
+; CHECK-NEXT: shll $9, %edi
+; CHECK-NEXT: cmpl %edi, %eax
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: retq
+ %and = and i32 %x, -1024
+ %sh = shl i32 %x, 9
+ %r = icmp eq i32 %and, %sh
+ ret i1 %r
+}
+
+define i1 @shl_to_shr_eq_i32_s9_fail_doesnt_add_up3(i32 %x) {
+; CHECK-LABEL: shl_to_shr_eq_i32_s9_fail_doesnt_add_up3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: andl $-256, %eax
+; CHECK-NEXT: shll $9, %edi
+; CHECK-NEXT: cmpl %edi, %eax
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: retq
+ %and = and i32 %x, -256
+ %sh = shl i32 %x, 9
+ %r = icmp eq i32 %and, %sh
+ ret i1 %r
+}
+
+define i1 @shl_to_shr_eq_i32_s9_fail_not_mask(i32 %x) {
+; CHECK-LABEL: shl_to_shr_eq_i32_s9_fail_not_mask:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: andl $-511, %eax # imm = 0xFE01
+; CHECK-NEXT: shll $9, %edi
+; CHECK-NEXT: cmpl %edi, %eax
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: retq
+ %and = and i32 %x, -511
+ %sh = shl i32 %x, 9
+ %r = icmp eq i32 %and, %sh
+ ret i1 %r
+}
+
+define i1 @shl_to_shr_eq_i32_s9_fail_not_mask2(i32 %x) {
+; CHECK-LABEL: shl_to_shr_eq_i32_s9_fail_not_mask2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: andl $-255, %eax
+; CHECK-NEXT: shll $9, %edi
+; CHECK-NEXT: cmpl %edi, %eax
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: retq
+ %and = and i32 %x, -255
+ %sh = shl i32 %x, 9
+ %r = icmp eq i32 %and, %sh
+ ret i1 %r
+}
+
+define i1 @shl_to_shr_eq_i32_s9_fail_wrong_mask2(i32 %x) {
+; CHECK-LABEL: shl_to_shr_eq_i32_s9_fail_wrong_mask2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: andl $8388607, %eax # imm = 0x7FFFFF
+; CHECK-NEXT: shll $9, %edi
+; CHECK-NEXT: cmpl %edi, %eax
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: retq
+ %and = and i32 %x, 8388607
+ %sh = shl i32 %x, 9
+ %r = icmp eq i32 %and, %sh
+ ret i1 %r
+}
+
+define i1 @shl_to_shr_eq_i32_s9(i32 %x) {
+; CHECK-LABEL: shl_to_shr_eq_i32_s9:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: andl $-512, %eax # imm = 0xFE00
+; CHECK-NEXT: shll $9, %edi
+; CHECK-NEXT: cmpl %edi, %eax
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: retq
+ %and = and i32 %x, -512
+ %sh = shl i32 %x, 9
+ %r = icmp eq i32 %and, %sh
+ ret i1 %r
+}
+
+define i1 @shr_to_shl_eq_i32_s5(i32 %x) {
+; CHECK-LABEL: shr_to_shl_eq_i32_s5:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: andl $134217727, %eax # imm = 0x7FFFFFF
+; CHECK-NEXT: shrl $5, %edi
+; CHECK-NEXT: cmpl %edi, %eax
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: retq
+ %and = and i32 %x, 134217727
+ %sh = lshr i32 %x, 5
+ %r = icmp eq i32 %and, %sh
+ ret i1 %r
+}
+
+define i1 @shr_to_rotate_eq_i32_s5(i32 %x) {
+; CHECK-LABEL: shr_to_rotate_eq_i32_s5:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: andl $268435455, %eax # imm = 0xFFFFFFF
+; CHECK-NEXT: shrl $4, %edi
+; CHECK-NEXT: cmpl %edi, %eax
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: retq
+ %and = and i32 %x, 268435455
+ %sh = lshr i32 %x, 4
+ %r = icmp eq i32 %and, %sh
+ ret i1 %r
+}
+
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK-AVX: {{.*}}
; CHECK-NOBMI-SSE2: {{.*}}
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