[llvm] [MachinePipeliner] Fix store-store dependences (#72508) (PR #72575)

[via llvm-commits]

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@@ -2251,7 +2251,13 @@ bool SwingSchedulerDAG::isLoopCarriedDep(SUnit *Source, const SDep &Dep,
       SI->hasOrderedMemoryRef() || DI->hasOrderedMemoryRef())
     return true;
 
-  // Only chain dependences between a load and store can be loop carried.
+  // Dependences between stores are loop carried to ensure that the dependent
+  // store is not scheduled after the source store on the next iteration.
+  if (Dep.isNormalMemory() && DI->mayStore() && SI->mayStore())
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mmarjieh wrote:

If two stores do not alias, Might there be a dependency of Order/Output between them?
If the answer is yes, then maybe we are too conservative.

https://github.com/llvm/llvm-project/pull/72575