[llvm] [AArch64] Allow LDR merge with same destination register by renaming (PR #71908)

[David Green via llvm-commits]

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@@ -926,31 +938,51 @@ AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
                 assert((MOP.isImplicit() ||
                         (MOP.isRenamable() && !MOP.isEarlyClobber())) &&
                            "Need renamable operands");
-                const TargetRegisterClass *RC =
-                    MI.getRegClassConstraint(OpIdx, TII, TRI);
-                if (!RC)
-                  continue;
-                MOP.setReg(GetMatchingSubReg(RC));
+                Register MatchingReg;
+                if (const TargetRegisterClass *RC =
+                        MI.getRegClassConstraint(OpIdx, TII, TRI))
+                  MatchingReg = GetMatchingSubReg(RC);
+                else
+                  MatchingReg = GetMatchingSubReg(
+                      TRI->getMinimalPhysRegClass(MOP.getReg()));
+                if (MatchingReg == AArch64::NoRegister)
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davemgreen wrote:

This can be an assert, as opposed to a if with a report_fatal_error.

https://github.com/llvm/llvm-project/pull/71908