[llvm] [InstCombine] Set disjoint flag when turning Add into Or. (PR #72702)

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``````````bash
git-clang-format --diff becd1cb9d3dfc8a962ec2e4b3fe373de1abce9ba 94871a9d27fa1b79b43f61acae6451e71a2c9725 -- llvm/include/llvm/AsmParser/LLToken.h llvm/include/llvm/Bitcode/LLVMBitCodes.h llvm/include/llvm/IR/InstrTypes.h llvm/include/llvm/IR/Instruction.h llvm/lib/AsmParser/LLLexer.cpp llvm/lib/AsmParser/LLParser.cpp llvm/lib/Bitcode/Reader/BitcodeReader.cpp llvm/lib/Bitcode/Writer/BitcodeWriter.cpp llvm/lib/IR/AsmWriter.cpp llvm/lib/IR/Instruction.cpp llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/AsmParser/LLParser.cpp b/llvm/lib/AsmParser/LLParser.cpp
index 0c170d8da9..aa2c80e5f0 100644
--- a/llvm/lib/AsmParser/LLParser.cpp
+++ b/llvm/lib/AsmParser/LLParser.cpp
@@ -2066,7 +2066,9 @@ bool LLParser::parseOptionalCallingConv(unsigned &CC) {
     break;
   case lltok::kw_amdgpu_kernel:  CC = CallingConv::AMDGPU_KERNEL; break;
   case lltok::kw_tailcc:         CC = CallingConv::Tail; break;
-  case lltok::kw_m68k_rtdcc:     CC = CallingConv::M68k_RTD; break;
+  case lltok::kw_m68k_rtdcc:
+    CC = CallingConv::M68k_RTD;
+    break;
   case lltok::kw_cc: {
       Lex.Lex();
       return parseUInt32(CC);
@@ -6372,7 +6374,8 @@ int LLParser::parseInstruction(Instruction *&Inst, BasicBlock *BB,
     bool Disjoint = EatIfPresent(lltok::kw_disjoint);
     if (parseLogical(Inst, PFS, KeywordVal))
       return true;
-    if (Disjoint) cast<PossiblyDisjointInst>(Inst)->setIsDisjoint(true);
+    if (Disjoint)
+      cast<PossiblyDisjointInst>(Inst)->setIsDisjoint(true);
     return false;
   }
   case lltok::kw_and:
diff --git a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
index e5aaa56f57..3e21a1a072 100644
--- a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
+++ b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
@@ -4878,7 +4878,6 @@ Error BitcodeReader::parseFunctionBody(Function *F) {
           if (FMF.any())
             I->setFastMathFlags(FMF);
         }
-
       }
       break;
     }
diff --git a/llvm/lib/IR/AsmWriter.cpp b/llvm/lib/IR/AsmWriter.cpp
index 688f1d7e07..95673eb364 100644
--- a/llvm/lib/IR/AsmWriter.cpp
+++ b/llvm/lib/IR/AsmWriter.cpp
@@ -306,7 +306,9 @@ static void PrintCallingConv(unsigned cc, raw_ostream &Out) {
   case CallingConv::PreserveAll:   Out << "preserve_allcc"; break;
   case CallingConv::CXX_FAST_TLS:  Out << "cxx_fast_tlscc"; break;
   case CallingConv::GHC:           Out << "ghccc"; break;
-  case CallingConv::Tail:          Out << "tailcc"; break;
+  case CallingConv::Tail:
+    Out << "tailcc";
+    break;
   case CallingConv::CFGuard_Check: Out << "cfguard_checkcc"; break;
   case CallingConv::X86_StdCall:   Out << "x86_stdcallcc"; break;
   case CallingConv::X86_FastCall:  Out << "x86_fastcallcc"; break;
@@ -1356,7 +1358,7 @@ static void WriteOptimizationInfo(raw_ostream &Out, const User *U) {
     if (Div->isExact())
       Out << " exact";
   } else if (const PossiblyDisjointInst *PDI =
-               dyn_cast<PossiblyDisjointInst>(U)) {
+                 dyn_cast<PossiblyDisjointInst>(U)) {
     if (PDI->isDisjoint())
       Out << " disjoint";
   } else if (const GEPOperator *GEP = dyn_cast<GEPOperator>(U)) {
diff --git a/llvm/lib/IR/Instruction.cpp b/llvm/lib/IR/Instruction.cpp
index fcf79f6cd8..4163a179d5 100644
--- a/llvm/lib/IR/Instruction.cpp
+++ b/llvm/lib/IR/Instruction.cpp
@@ -319,8 +319,9 @@ void Instruction::setIsExact(bool b) {
 
 void Instruction::setIsDisjoint(bool b) {
   assert(isa<PossiblyDisjointInst>(this) && "Must be or");
-  SubclassOptionalData = (SubclassOptionalData & ~PossiblyDisjointInst::IsDisjoint) |
-                         (b * PossiblyDisjointInst::IsDisjoint);
+  SubclassOptionalData =
+      (SubclassOptionalData & ~PossiblyDisjointInst::IsDisjoint) |
+      (b * PossiblyDisjointInst::IsDisjoint);
 }
 
 void Instruction::setNonNeg(bool b) {

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https://github.com/llvm/llvm-project/pull/72702