[llvm] [ValueTracking] Ignore poison values in `computeKnownBits` (PR #72683)
Yingwei Zheng via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 17 10:00:02 PST 2023
https://github.com/dtcxzyw created https://github.com/llvm/llvm-project/pull/72683
This patch handles `poison` elements of non-splat vectors in `computeKnownBits`. It addresses test changes after I delete the duplicate logic in https://github.com/llvm/llvm-project/pull/72535.
See also @nikic's comment: https://github.com/llvm/llvm-project/pull/72535#pullrequestreview-1736991557
This missed optimization is discovered with the help of https://github.com/AliveToolkit/alive2/pull/962.
BTW, alive2 also reports some missed optimizations with `undef` elements in non-splat vectors. I have no idea how to handle it correctly. Just ignoring `undef` doesn't work.
>From 8e62bb7d4499a60230796f28adc871b57ff17015 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Sat, 18 Nov 2023 01:41:42 +0800
Subject: [PATCH] [ValueTracking] Ignore poison values in `computeKnownBits`
---
llvm/lib/Analysis/ValueTracking.cpp | 2 +
.../X86/x86-vector-shifts-inseltpoison.ll | 44 +++++++++----------
llvm/test/Transforms/InstCombine/add.ll | 2 +-
.../Transforms/InstCombine/extractelement.ll | 2 +-
llvm/test/Transforms/InstCombine/lshr.ll | 4 +-
llvm/test/Transforms/InstCombine/mul.ll | 6 +--
6 files changed, 30 insertions(+), 30 deletions(-)
diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp
index 5f5d7e07cac1e46..206be912f4b9fe9 100644
--- a/llvm/lib/Analysis/ValueTracking.cpp
+++ b/llvm/lib/Analysis/ValueTracking.cpp
@@ -1889,6 +1889,8 @@ void computeKnownBits(const Value *V, const APInt &DemandedElts,
if (!DemandedElts[i])
continue;
Constant *Element = CV->getAggregateElement(i);
+ if (isa<PoisonValue>(Element))
+ continue;
auto *ElementCI = dyn_cast_or_null<ConstantInt>(Element);
if (!ElementCI) {
Known.resetAll();
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-vector-shifts-inseltpoison.ll b/llvm/test/Transforms/InstCombine/X86/x86-vector-shifts-inseltpoison.ll
index 21d5723cbb82d63..5b6ce56b4b3265f 100644
--- a/llvm/test/Transforms/InstCombine/X86/x86-vector-shifts-inseltpoison.ll
+++ b/llvm/test/Transforms/InstCombine/X86/x86-vector-shifts-inseltpoison.ll
@@ -1710,7 +1710,7 @@ define <4 x i64> @avx512_psrav_q_256_allbig(<4 x i64> %v) {
define <2 x i64> @avx512_psrav_q_128_poison(<2 x i64> %v) {
; CHECK-LABEL: @avx512_psrav_q_128_poison(
-; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i64> [[V:%.*]], <i64 undef, i64 8>
+; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i64> [[V:%.*]], <i64 poison, i64 8>
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
;
%1 = insertelement <2 x i64> <i64 0, i64 8>, i64 poison, i64 0
@@ -1720,7 +1720,7 @@ define <2 x i64> @avx512_psrav_q_128_poison(<2 x i64> %v) {
define <4 x i64> @avx512_psrav_q_256_poison(<4 x i64> %v) {
; CHECK-LABEL: @avx512_psrav_q_256_poison(
-; CHECK-NEXT: [[TMP1:%.*]] = ashr <4 x i64> [[V:%.*]], <i64 undef, i64 8, i64 16, i64 31>
+; CHECK-NEXT: [[TMP1:%.*]] = ashr <4 x i64> [[V:%.*]], <i64 poison, i64 8, i64 16, i64 31>
; CHECK-NEXT: ret <4 x i64> [[TMP1]]
;
%1 = insertelement <4 x i64> <i64 0, i64 8, i64 16, i64 31>, i64 poison, i64 0
@@ -1756,7 +1756,7 @@ define <8 x i64> @avx512_psrav_q_512_allbig(<8 x i64> %v) {
define <8 x i64> @avx512_psrav_q_512_poison(<8 x i64> %v) {
; CHECK-LABEL: @avx512_psrav_q_512_poison(
-; CHECK-NEXT: [[TMP1:%.*]] = ashr <8 x i64> [[V:%.*]], <i64 undef, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>
+; CHECK-NEXT: [[TMP1:%.*]] = ashr <8 x i64> [[V:%.*]], <i64 poison, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>
; CHECK-NEXT: ret <8 x i64> [[TMP1]]
;
%1 = insertelement <8 x i64> <i64 0, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>, i64 poison, i64 0
@@ -1792,7 +1792,7 @@ define <8 x i16> @avx512_psrav_w_128_allbig(<8 x i16> %v) {
define <8 x i16> @avx512_psrav_w_128_poison(<8 x i16> %v) {
; CHECK-LABEL: @avx512_psrav_w_128_poison(
-; CHECK-NEXT: [[TMP1:%.*]] = ashr <8 x i16> [[V:%.*]], <i16 undef, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; CHECK-NEXT: [[TMP1:%.*]] = ashr <8 x i16> [[V:%.*]], <i16 poison, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
; CHECK-NEXT: ret <8 x i16> [[TMP1]]
;
%1 = insertelement <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, i16 poison, i64 0
@@ -1828,7 +1828,7 @@ define <16 x i16> @avx512_psrav_w_256_allbig(<16 x i16> %v) {
define <16 x i16> @avx512_psrav_w_256_poison(<16 x i16> %v) {
; CHECK-LABEL: @avx512_psrav_w_256_poison(
-; CHECK-NEXT: [[TMP1:%.*]] = ashr <16 x i16> [[V:%.*]], <i16 undef, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
+; CHECK-NEXT: [[TMP1:%.*]] = ashr <16 x i16> [[V:%.*]], <i16 poison, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
; CHECK-NEXT: ret <16 x i16> [[TMP1]]
;
%1 = insertelement <16 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, i16 poison, i64 0
@@ -1864,7 +1864,7 @@ define <32 x i16> @avx512_psrav_w_512_allbig(<32 x i16> %v) {
define <32 x i16> @avx512_psrav_w_512_poison(<32 x i16> %v) {
; CHECK-LABEL: @avx512_psrav_w_512_poison(
-; CHECK-NEXT: [[TMP1:%.*]] = ashr <32 x i16> [[V:%.*]], <i16 undef, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>
+; CHECK-NEXT: [[TMP1:%.*]] = ashr <32 x i16> [[V:%.*]], <i16 poison, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>
; CHECK-NEXT: ret <32 x i16> [[TMP1]]
;
%1 = insertelement <32 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 poison, i64 0
@@ -1946,7 +1946,7 @@ define <8 x i32> @avx2_psrlv_d_256_allbig(<8 x i32> %v) {
define <4 x i32> @avx2_psrlv_d_128_poison(<4 x i32> %v) {
; CHECK-LABEL: @avx2_psrlv_d_128_poison(
-; CHECK-NEXT: [[TMP1:%.*]] = lshr <4 x i32> [[V:%.*]], <i32 undef, i32 8, i32 16, i32 31>
+; CHECK-NEXT: [[TMP1:%.*]] = lshr <4 x i32> [[V:%.*]], <i32 poison, i32 8, i32 16, i32 31>
; CHECK-NEXT: ret <4 x i32> [[TMP1]]
;
%1 = insertelement <4 x i32> <i32 0, i32 8, i32 16, i32 31>, i32 poison, i32 0
@@ -1956,7 +1956,7 @@ define <4 x i32> @avx2_psrlv_d_128_poison(<4 x i32> %v) {
define <8 x i32> @avx2_psrlv_d_256_poison(<8 x i32> %v) {
; CHECK-LABEL: @avx2_psrlv_d_256_poison(
-; CHECK-NEXT: [[TMP1:%.*]] = lshr <8 x i32> [[V:%.*]], <i32 0, i32 undef, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>
+; CHECK-NEXT: [[TMP1:%.*]] = lshr <8 x i32> [[V:%.*]], <i32 0, i32 poison, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>
; CHECK-NEXT: ret <8 x i32> [[TMP1]]
;
%1 = insertelement <8 x i32> <i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>, i32 poison, i32 1
@@ -2045,7 +2045,7 @@ define <2 x i64> @avx2_psrlv_q_128_poison(<2 x i64> %v) {
define <4 x i64> @avx2_psrlv_q_256_poison(<4 x i64> %v) {
; CHECK-LABEL: @avx2_psrlv_q_256_poison(
-; CHECK-NEXT: [[TMP1:%.*]] = lshr <4 x i64> [[V:%.*]], <i64 undef, i64 8, i64 16, i64 31>
+; CHECK-NEXT: [[TMP1:%.*]] = lshr <4 x i64> [[V:%.*]], <i64 poison, i64 8, i64 16, i64 31>
; CHECK-NEXT: ret <4 x i64> [[TMP1]]
;
%1 = insertelement <4 x i64> <i64 0, i64 8, i64 16, i64 31>, i64 poison, i64 0
@@ -2089,7 +2089,7 @@ define <16 x i32> @avx512_psrlv_d_512_allbig(<16 x i32> %v) {
define <16 x i32> @avx512_psrlv_d_512_poison(<16 x i32> %v) {
; CHECK-LABEL: @avx512_psrlv_d_512_poison(
-; CHECK-NEXT: [[TMP1:%.*]] = lshr <16 x i32> [[V:%.*]], <i32 0, i32 undef, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>
+; CHECK-NEXT: [[TMP1:%.*]] = lshr <16 x i32> [[V:%.*]], <i32 0, i32 poison, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>
; CHECK-NEXT: ret <16 x i32> [[TMP1]]
;
%1 = insertelement <16 x i32> <i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>, i32 poison, i32 1
@@ -2133,7 +2133,7 @@ define <8 x i64> @avx512_psrlv_q_512_allbig(<8 x i64> %v) {
define <8 x i64> @avx512_psrlv_q_512_poison(<8 x i64> %v) {
; CHECK-LABEL: @avx512_psrlv_q_512_poison(
-; CHECK-NEXT: [[TMP1:%.*]] = lshr <8 x i64> [[V:%.*]], <i64 undef, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>
+; CHECK-NEXT: [[TMP1:%.*]] = lshr <8 x i64> [[V:%.*]], <i64 poison, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>
; CHECK-NEXT: ret <8 x i64> [[TMP1]]
;
%1 = insertelement <8 x i64> <i64 0, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>, i64 poison, i64 0
@@ -2177,7 +2177,7 @@ define <8 x i16> @avx512_psrlv_w_128_allbig(<8 x i16> %v) {
define <8 x i16> @avx512_psrlv_w_128_poison(<8 x i16> %v) {
; CHECK-LABEL: @avx512_psrlv_w_128_poison(
-; CHECK-NEXT: [[TMP1:%.*]] = lshr <8 x i16> [[V:%.*]], <i16 undef, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; CHECK-NEXT: [[TMP1:%.*]] = lshr <8 x i16> [[V:%.*]], <i16 poison, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
; CHECK-NEXT: ret <8 x i16> [[TMP1]]
;
%1 = insertelement <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, i16 poison, i64 0
@@ -2221,7 +2221,7 @@ define <16 x i16> @avx512_psrlv_w_256_allbig(<16 x i16> %v) {
define <16 x i16> @avx512_psrlv_w_256_poison(<16 x i16> %v) {
; CHECK-LABEL: @avx512_psrlv_w_256_poison(
-; CHECK-NEXT: [[TMP1:%.*]] = lshr <16 x i16> [[V:%.*]], <i16 undef, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
+; CHECK-NEXT: [[TMP1:%.*]] = lshr <16 x i16> [[V:%.*]], <i16 poison, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
; CHECK-NEXT: ret <16 x i16> [[TMP1]]
;
%1 = insertelement <16 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, i16 poison, i64 0
@@ -2265,7 +2265,7 @@ define <32 x i16> @avx512_psrlv_w_512_allbig(<32 x i16> %v) {
define <32 x i16> @avx512_psrlv_w_512_poison(<32 x i16> %v) {
; CHECK-LABEL: @avx512_psrlv_w_512_poison(
-; CHECK-NEXT: [[TMP1:%.*]] = lshr <32 x i16> [[V:%.*]], <i16 undef, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>
+; CHECK-NEXT: [[TMP1:%.*]] = lshr <32 x i16> [[V:%.*]], <i16 poison, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>
; CHECK-NEXT: ret <32 x i16> [[TMP1]]
;
%1 = insertelement <32 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 poison, i64 0
@@ -2347,7 +2347,7 @@ define <8 x i32> @avx2_psllv_d_256_allbig(<8 x i32> %v) {
define <4 x i32> @avx2_psllv_d_128_poison(<4 x i32> %v) {
; CHECK-LABEL: @avx2_psllv_d_128_poison(
-; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i32> [[V:%.*]], <i32 undef, i32 8, i32 16, i32 31>
+; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i32> [[V:%.*]], <i32 poison, i32 8, i32 16, i32 31>
; CHECK-NEXT: ret <4 x i32> [[TMP1]]
;
%1 = insertelement <4 x i32> <i32 0, i32 8, i32 16, i32 31>, i32 poison, i32 0
@@ -2357,7 +2357,7 @@ define <4 x i32> @avx2_psllv_d_128_poison(<4 x i32> %v) {
define <8 x i32> @avx2_psllv_d_256_poison(<8 x i32> %v) {
; CHECK-LABEL: @avx2_psllv_d_256_poison(
-; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> [[V:%.*]], <i32 0, i32 undef, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>
+; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> [[V:%.*]], <i32 0, i32 poison, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>
; CHECK-NEXT: ret <8 x i32> [[TMP1]]
;
%1 = insertelement <8 x i32> <i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>, i32 poison, i32 1
@@ -2446,7 +2446,7 @@ define <2 x i64> @avx2_psllv_q_128_poison(<2 x i64> %v) {
define <4 x i64> @avx2_psllv_q_256_poison(<4 x i64> %v) {
; CHECK-LABEL: @avx2_psllv_q_256_poison(
-; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i64> [[V:%.*]], <i64 undef, i64 8, i64 16, i64 31>
+; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i64> [[V:%.*]], <i64 poison, i64 8, i64 16, i64 31>
; CHECK-NEXT: ret <4 x i64> [[TMP1]]
;
%1 = insertelement <4 x i64> <i64 0, i64 8, i64 16, i64 31>, i64 poison, i64 0
@@ -2490,7 +2490,7 @@ define <16 x i32> @avx512_psllv_d_512_allbig(<16 x i32> %v) {
define <16 x i32> @avx512_psllv_d_512_poison(<16 x i32> %v) {
; CHECK-LABEL: @avx512_psllv_d_512_poison(
-; CHECK-NEXT: [[TMP1:%.*]] = shl <16 x i32> [[V:%.*]], <i32 0, i32 undef, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>
+; CHECK-NEXT: [[TMP1:%.*]] = shl <16 x i32> [[V:%.*]], <i32 0, i32 poison, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>
; CHECK-NEXT: ret <16 x i32> [[TMP1]]
;
%1 = insertelement <16 x i32> <i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>, i32 poison, i32 1
@@ -2534,7 +2534,7 @@ define <8 x i64> @avx512_psllv_q_512_allbig(<8 x i64> %v) {
define <8 x i64> @avx512_psllv_q_512_poison(<8 x i64> %v) {
; CHECK-LABEL: @avx512_psllv_q_512_poison(
-; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i64> [[V:%.*]], <i64 undef, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>
+; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i64> [[V:%.*]], <i64 poison, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>
; CHECK-NEXT: ret <8 x i64> [[TMP1]]
;
%1 = insertelement <8 x i64> <i64 0, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>, i64 poison, i64 0
@@ -2578,7 +2578,7 @@ define <8 x i16> @avx512_psllv_w_128_allbig(<8 x i16> %v) {
define <8 x i16> @avx512_psllv_w_128_poison(<8 x i16> %v) {
; CHECK-LABEL: @avx512_psllv_w_128_poison(
-; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i16> [[V:%.*]], <i16 undef, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i16> [[V:%.*]], <i16 poison, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
; CHECK-NEXT: ret <8 x i16> [[TMP1]]
;
%1 = insertelement <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, i16 poison, i64 0
@@ -2622,7 +2622,7 @@ define <16 x i16> @avx512_psllv_w_256_allbig(<16 x i16> %v) {
define <16 x i16> @avx512_psllv_w_256_poison(<16 x i16> %v) {
; CHECK-LABEL: @avx512_psllv_w_256_poison(
-; CHECK-NEXT: [[TMP1:%.*]] = shl <16 x i16> [[V:%.*]], <i16 undef, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
+; CHECK-NEXT: [[TMP1:%.*]] = shl <16 x i16> [[V:%.*]], <i16 poison, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
; CHECK-NEXT: ret <16 x i16> [[TMP1]]
;
%1 = insertelement <16 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, i16 poison, i64 0
@@ -2666,7 +2666,7 @@ define <32 x i16> @avx512_psllv_w_512_allbig(<32 x i16> %v) {
define <32 x i16> @avx512_psllv_w_512_poison(<32 x i16> %v) {
; CHECK-LABEL: @avx512_psllv_w_512_poison(
-; CHECK-NEXT: [[TMP1:%.*]] = shl <32 x i16> [[V:%.*]], <i16 undef, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>
+; CHECK-NEXT: [[TMP1:%.*]] = shl <32 x i16> [[V:%.*]], <i16 poison, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>
; CHECK-NEXT: ret <32 x i16> [[TMP1]]
;
%1 = insertelement <32 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 poison, i64 0
diff --git a/llvm/test/Transforms/InstCombine/add.ll b/llvm/test/Transforms/InstCombine/add.ll
index 2ae0181974bf8a6..e20da141742adf2 100644
--- a/llvm/test/Transforms/InstCombine/add.ll
+++ b/llvm/test/Transforms/InstCombine/add.ll
@@ -3037,7 +3037,7 @@ define <2 x i32> @dec_zext_add_nonzero_vec_poison2(<2 x i8> %x) {
; CHECK-NEXT: [[O:%.*]] = or <2 x i8> [[X:%.*]], <i8 8, i8 8>
; CHECK-NEXT: [[A:%.*]] = add nsw <2 x i8> [[O]], <i8 -1, i8 -1>
; CHECK-NEXT: [[B:%.*]] = zext <2 x i8> [[A]] to <2 x i32>
-; CHECK-NEXT: [[C:%.*]] = add <2 x i32> [[B]], <i32 1, i32 poison>
+; CHECK-NEXT: [[C:%.*]] = add nuw nsw <2 x i32> [[B]], <i32 1, i32 poison>
; CHECK-NEXT: ret <2 x i32> [[C]]
;
%o = or <2 x i8> %x, <i8 8, i8 8>
diff --git a/llvm/test/Transforms/InstCombine/extractelement.ll b/llvm/test/Transforms/InstCombine/extractelement.ll
index 1e8b995a5bc025c..540a4c7d1722a68 100644
--- a/llvm/test/Transforms/InstCombine/extractelement.ll
+++ b/llvm/test/Transforms/InstCombine/extractelement.ll
@@ -819,7 +819,7 @@ define i32 @extelt_select_const_operand_select_use(i1 %c) {
; ANY-NEXT: [[S:%.*]] = select i1 [[C:%.*]], <3 x i32> <i32 poison, i32 3, i32 4>, <3 x i32> <i32 poison, i32 6, i32 7>
; ANY-NEXT: [[E:%.*]] = extractelement <3 x i32> [[S]], i64 2
; ANY-NEXT: [[E_2:%.*]] = extractelement <3 x i32> [[S]], i64 1
-; ANY-NEXT: [[R:%.*]] = mul i32 [[E]], [[E_2]]
+; ANY-NEXT: [[R:%.*]] = mul nuw nsw i32 [[E]], [[E_2]]
; ANY-NEXT: ret i32 [[R]]
;
%s = select i1 %c, <3 x i32> <i32 2, i32 3, i32 4>, <3 x i32> <i32 5, i32 6, i32 7>
diff --git a/llvm/test/Transforms/InstCombine/lshr.ll b/llvm/test/Transforms/InstCombine/lshr.ll
index 56d7cf5f452ce8a..02c2bbc2819b8cf 100644
--- a/llvm/test/Transforms/InstCombine/lshr.ll
+++ b/llvm/test/Transforms/InstCombine/lshr.ll
@@ -889,13 +889,11 @@ define <2 x i64> @narrow_bswap_splat(<2 x i16> %x) {
ret <2 x i64> %s
}
-; TODO: poison/undef in the shift amount is ok to propagate.
-
define <2 x i64> @narrow_bswap_splat_poison_elt(<2 x i16> %x) {
; CHECK-LABEL: @narrow_bswap_splat_poison_elt(
; CHECK-NEXT: [[Z:%.*]] = zext <2 x i16> [[X:%.*]] to <2 x i64>
; CHECK-NEXT: [[B:%.*]] = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> [[Z]])
-; CHECK-NEXT: [[S:%.*]] = lshr <2 x i64> [[B]], <i64 48, i64 poison>
+; CHECK-NEXT: [[S:%.*]] = lshr exact <2 x i64> [[B]], <i64 48, i64 poison>
; CHECK-NEXT: ret <2 x i64> [[S]]
;
%z = zext <2 x i16> %x to <2 x i64>
diff --git a/llvm/test/Transforms/InstCombine/mul.ll b/llvm/test/Transforms/InstCombine/mul.ll
index 55092e93d09274b..42698b5102bc5b7 100644
--- a/llvm/test/Transforms/InstCombine/mul.ll
+++ b/llvm/test/Transforms/InstCombine/mul.ll
@@ -981,8 +981,8 @@ define <2 x i32> @PR57278_shl_vec(<2 x i32> %v1) {
define <2 x i32> @PR57278_shl_vec_poison(<2 x i32> %v1) {
; CHECK-LABEL: @PR57278_shl_vec_poison(
; CHECK-NEXT: [[SHL:%.*]] = shl nuw <2 x i32> [[V1:%.*]], <i32 2, i32 poison>
-; CHECK-NEXT: [[ADD:%.*]] = or <2 x i32> [[SHL]], <i32 3, i32 poison>
-; CHECK-NEXT: [[MUL:%.*]] = mul nuw <2 x i32> [[ADD]], <i32 3, i32 poison>
+; CHECK-NEXT: [[TMP1:%.*]] = mul nuw <2 x i32> [[SHL]], <i32 3, i32 poison>
+; CHECK-NEXT: [[MUL:%.*]] = add nuw <2 x i32> [[TMP1]], <i32 9, i32 poison>
; CHECK-NEXT: ret <2 x i32> [[MUL]]
;
%shl = shl nuw <2 x i32> %v1, <i32 2, i32 poison>
@@ -1765,7 +1765,7 @@ define <2 x i16> @sext_negpow2_vec(<2 x i8> %x) {
define <2 x i16> @sext_negpow2_too_small_vec(<2 x i8> %x) {
; CHECK-LABEL: @sext_negpow2_too_small_vec(
; CHECK-NEXT: [[SX:%.*]] = sext <2 x i8> [[X:%.*]] to <2 x i16>
-; CHECK-NEXT: [[R:%.*]] = mul <2 x i16> [[SX]], <i16 -128, i16 poison>
+; CHECK-NEXT: [[R:%.*]] = mul nsw <2 x i16> [[SX]], <i16 -128, i16 poison>
; CHECK-NEXT: ret <2 x i16> [[R]]
;
%sx = sext <2 x i8> %x to <2 x i16>
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