[llvm] 58253dc - [X86] getTargetConstantBitsFromNode - bail if we're loading from a constant vector element type larger than the target value size

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2023-11-17T10:01:31Z
New Revision: 58253dcbcdfafb1fb1fb5ffc43d6f11a31f35e2a

URL: https://github.com/llvm/llvm-project/commit/58253dcbcdfafb1fb1fb5ffc43d6f11a31f35e2a
DIFF: https://github.com/llvm/llvm-project/commit/58253dcbcdfafb1fb1fb5ffc43d6f11a31f35e2a.diff

LOG: [X86] getTargetConstantBitsFromNode - bail if we're loading from a constant vector element type larger than the target value size

This can be improved upon by just truncating the constant value, but the crash needs to be addressed first.

Fixes #72539

Added: 
    llvm/test/CodeGen/X86/pr72539.ll

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 7f9d971ceeeeaf6..cf667077e882a4f 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -4664,6 +4664,8 @@ static bool getTargetConstantBitsFromNode(SDValue Op, unsigned EltSizeInBits,
 
     unsigned SrcEltSizeInBits = CstTy->getScalarSizeInBits();
     unsigned NumSrcElts = SizeInBits / SrcEltSizeInBits;
+    if ((SizeInBits % SrcEltSizeInBits) != 0)
+      return false;
 
     APInt UndefSrcElts(NumSrcElts, 0);
     SmallVector<APInt, 64> SrcEltBits(NumSrcElts, APInt(SrcEltSizeInBits, 0));

diff  --git a/llvm/test/CodeGen/X86/pr72539.ll b/llvm/test/CodeGen/X86/pr72539.ll
new file mode 100644
index 000000000000000..fb4c98dca8cee4d
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr72539.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64    | FileCheck %s --check-prefixes=SSE
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=SSE
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=AVX
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX
+
+define void @PR72539(<8 x i32> %insertelement){
+; SSE-LABEL: PR72539:
+; SSE:       # %bb.0:
+; SSE-NEXT:    xorb $7, 0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: PR72539:
+; AVX:       # %bb.0:
+; AVX-NEXT:    movzbl {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %eax
+; AVX-NEXT:    xorb %al, 0
+; AVX-NEXT:    retq
+  %load671 = load i8, ptr addrspace(1) null, align 1
+  %shufflevector = shufflevector <8 x i32> %insertelement, <8 x i32> zeroinitializer, <8 x i32> zeroinitializer
+  %xor68 = xor <8 x i32> %shufflevector, <i32 7, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
+  %call69 = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> %xor68)
+  %trunc70 = trunc i32 %call69 to i8
+  %xor71 = xor i8 %load671, %trunc70
+  store i8 %xor71, ptr addrspace(1) null, align 1
+  ret void
+}
+declare i32 @llvm.vector.reduce.xor.v8i32(<8 x i32>)