[llvm] [AMDGPU] Allocate i1 argument to SGPRs (PR #72461)

[Matt Arsenault via llvm-commits]

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@@ -185,9 +185,12 @@ def CSR_AMDGPU_NoRegs : CalleeSavedRegs<(add)>;
 // Calling convention for leaf functions
 def CC_AMDGPU_Func : CallingConv<[
   CCIfByVal<CCPassByVal<4, 4>>,
-  CCIfType<[i1], CCPromoteToType<i32>>,
   CCIfType<[i8, i16], CCIfExtend<CCPromoteToType<i32>>>,
 
+  CCIfType<[i1] , CCAssignToReg<
+    !foreach(i, !range(0, 30), !cast<Register>("SGPR"#i))  // SGPR0-29
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arsenm wrote:

This isn't really right, the register used differs based on the wavesize. i.e. wave32 should start at s0, and wave64 would use s[0:1] (ignoring the registers used for the SRD of course).

This may require some hacking around in the lowering code. We may also need to define separate wave size calling CallingConv variants 

https://github.com/llvm/llvm-project/pull/72461