[llvm] [AArch64] merge index address with large offset into base address (PR #72187)

[via llvm-commits]

vfdff wrote:

> This seems like it would be simpler to do at the point where we're computing the addressing mode in the first place (in ISelDAGToDAG).

Thanks for your idea @efriedma-quic
I tried to refactor it in `AArch64DAGToDAGISel::SelectAddrModeXRO` according your idea, and find  I can only modify the **Base** and **Offset** of the load/store instruction.
Therefore, the following format is generated after the adjustment. The instruction LDRWroX here requires [reg + reg], so an error is reported, Is there a way to adjust the opcode?
```
%1:gpr32 = MOVi32imm 4160992
%2:gpr64 = SUBREG_TO_REG 0, killed %1:gpr32, %subreg.sub_32
%3:gpr32 = LDRWroX %0:gpr64common, %2:gpr64, 0, 0
 ---> 
%1:gpr64sp = ADDXri %0:gpr64common, 1012, 12
%2:gpr32 = LDRWroX killed %1:gpr64sp, 15840, 0, 0  // The 2nd operand 15840 required a reg
```

https://github.com/llvm/llvm-project/pull/72187